LSM6DSMTR datasheet(38/113 Pages) STMICROELECTRONICS

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Digital interfaces

LSM6DSM

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6.3

Auxiliary SPI

If LSM6DSM is configured in Mode3, the auxiliary SPI is available. The auxiliary SPI

interface is mapped in the following dedicated pins.

6.4

I2C serial interface

The LSM6DSM I2C is a bus slave. The I2C is employed to write the data to the registers,

whose content can also be read back.

The relevant I2C terminology is provided in the table below.

There are two signals associated with the I2C bus: the serial clock line (SCL) and the Serial

DAta line (SDA). The latter is a bidirectional line used for sending and receiving the data

to/from the interface. Both the lines must be connected to Vdd_IO through external pull-up

resistors. When the bus is free, both the lines are high.

The I2C interface is implemeted with fast mode (400 kHz) I2C standards as well as with the

standard mode.

In order to disable the I2C block, (I2C_disable) = 1 must be written in CTRL4_C (13h).

6.4.1

I2C operation

The transaction on the bus is started through a START (ST) signal. A START condition is

defined as a HIGH to LOW transition on the data line while the SCL line is held HIGH. After

this has been transmitted by the master, the bus is considered busy. The next byte of data

transmitted after the start condition contains the address of the slave in the first 7 bits and

the eighth bit tells whether the master is receiving data from the slave or transmitting data to

the slave. When an address is sent, each device in the system compares the first seven bits

after a start condition with its address. If they match, the device considers itself addressed

by the master.

Table 11. Auxiliary SPI pin details

Pin name

Pin description

OCS_Aux

Auxiliary SPI 3/4-wire enable

SDx

Auxiliary SPI 3/4-wire data input (SDI_Aux) and SPI 3-wire data output (SDO_Aux)

SCx

Auxiliary SPI 3/4-wire interface serial port clock

SDO_Aux

SPI serial data

Table 12. I2C terminology

Term

Description

Transmitter

The device which sends data to the bus

Receiver

The device which receives data from the bus

Master

The device which initiates a transfer, generates clock signals and terminates a

transfer

Slave

The device addressed by the master

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