TUSB8041 datasheet(21/48 Pages) TI1

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TUSB8041

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SLLSEE4D – JUNE 2014 – REVISED JANUARY 2016

8.5.11 Device Configuration Register 2

Table 22. Register Offset Ah

Bit No.

Reset State

Table 23. Bit Descriptions – Device Configuration Register 2

Bit

Field Name

Access

Description

Reserved. Read-only, returns 0 when read.

Reserved

Custom Battery Charging Feature Enable. This bit controls the ability to

write to the battery charging feature configuration controls.

0 = The HiCurAcpModeEn and cpdEN bits are read only and the

values are loaded from the OTP ROM.

customBCfeatures

1 = The HiCurAcpModeEn and cpdEN, bits are read/write and can

be loaded by EEPROM or written by SMBus. from this register.

This bit may be written simultaneously with HiCurAcpModeEn and

cpdEN.

Power enable polarity. This bit is loaded at the de-assertion of reset with

the value of the PWRCTL_POL pin.

0 = PWRCTL polarity is active low

1 = PWRCTL polarity is active high

pwrctlPol

When the TUSB8041 is in I2C mode, the TUSB8041 loads this bit from

the contents of the EEPROM.

When the TUSB8041 is in SMBUS mode, the value may be over-written

by an SMBus host.

High-current ACP mode enable. This bit enables the high-current tablet

charging mode when the automatic battery charging mode is enabled for

downstream ports.

0 = High current divider mode disabled

HiCurAcpModeEn

RO/RW

1 = High current divider mode enabled

This bit is read only unless the customBCfeatures bit is set to 1. If

customBCfeatures is 0, the value of this bit reflects the value of the OTP

ROM HiCurAcpModeEn bit.

Enable Device Attach Detection. This bit enables device attach detection

(aka, cell phone detect) when autoMode is enabled.

0 = Device Attach detect is disabled in automode.

cpdEN

RORW

1 = Device Attach detect is enabled in automode..

This bit is read only unless the customBCfeatures bit is set to 1. If

customBCfeatures is 0 the value of this bit reflects the value of the OTP

ROM cpdEN bit.

DSPORT ECR Enable. This bit enables full implementation of the

DSPORT ECR (April 2013).

0 = The DSPORT ECR (April 2013) is enabled with exception of the

following: Changes related to when CCS bit is set upon entering U0,

dsportEcr_en

and Changes related to avoiding or reporting compliance mode entry

1 = The full DSPORT ECR (April 2013) is enabled.

The default value of this bit is 0. The value returned from this register will

be the OR of this bit and the OTP ROM dsport_ecr_en bit.

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