Unit LoadingFan Out

54F74F

Pin Names

Description

UL

Count Up Clock Input (Active Rising Edge)

1030

Count Down Clock Input (Active Rising Edge)

1030

MR

Asynchronous Master Reset Input (Active HIGH)

1010

PL

Asynchronous Parallel Load Input (Active LOW)

1010

Parallel Data Inputs

1010

Flip-Flop Outputs

50333

b

1 mA20 mA

Terminal Count Down (Borrow) Output (Active LOW)

50333

b

1 mA20 mA

Terminal Count Up (Carry) Output (Active LOW)

50333

b

1 mA20 mA

Functional Description

The ’F192 is an asynchronously presettable decade coun-

ter It contains four edge-triggered flip-flops with internal

gating and steering logic to provide master reset individual

preset count up and count down operations

A LOW-to-HIGH transition on the CP input to each flip-flop

causes the output to change state Synchronous switching

as opposed to ripple counting is achieved by driving the

steering gates of all stages from a common Count Up line

and a common Count Down line thereby causing all state

changes to be initiated simultaneously A LOW-to-HIGH

transition on the Count Up input will advance the count by

one a similar transition on the Count Down input will de-

crease the count by one While counting with one clock in-

put the other should be held HIGH as indicated in the

Function Table Otherwise the circuit will either count by

twos or not at all depending on the state of the first flip-flop

which cannot toggle as long as either clock input is LOW

reached the maximum count state 9 the next HIGH-to-LOW

tively repeating the Count Up Clock but delayed by two

circuit is in the zero state and the Count Down Clock goes

LOW Since the TC outputs repeat the clock waveforms

they can be used as the clock input signals to the next

higher order circuit in a multistage counter

The ’F192 has an asynchronous parallel load capability per-

mitting the counter to be preset When the Parallel Load

(PL) and the Master Reset (MR) inputs are LOW informa-

into the counter and appears on the outputs regardless of

the conditions of the clock inputs A HIGH signal on the

Master Reset input will disable the preset gates override

both clock inputs and latch each Q output in the LOW state

If one of the clock inputs is LOW during and after a reset or

load operation the next LOW-to-HIGH transition of that

clock will be interpreted as a legitimate signal and will be

counted

Function Table

MR

PL

Mode

H

X

X

X

Reset (Asyn)

L

L

X

X

Preset (Asyn)

L

H

H

H

No Change

LH

L

H

Count Up

LH

H

L

Count Down

State Diagram

TLF9496 – 4

2