Unused Input

Input

Output

Input

Unused Input

Output

11

SN54LVC00A, SN74LVC00A

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SCAS279R – JANUARY 1993 – REVISED FEBRUARY 2016

Product Folder Links: SN54LVC00A SN74LVC00A

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Copyright © 1993–2016, Texas Instruments Incorporated

Typical Application (continued)

10.2.3 Application Curves

11 Power Supply Recommendations

The power supply can be any voltage between the MIN and MAX supply voltage rating located in the

Recommended Operating Conditions, SN74LVC00A table.

supply, 0.1

each power pin. It is acceptable to parallel multiple bypass caps to reject different frequencies of noise. A 0.1

μF

and a 1

μF are commonly used in parallel. The bypass capacitor should be installed as close to the power pin as

possible for best results.

12 Layout

12.1 Layout Guidelines

When using multiple bit logic devices inputs should never float.

In many cases, functions or parts of functions of digital logic devices are unused, for example, when only two

inputs of a triple-input AND gate are used or only 3 of the 4 buffer gates are used. Such input pins should not be

left unconnected because the undefined voltages at the outside connections result in undefined operational

states. Layout Example specifies the rules that must be observed under all circumstances. All unused inputs of

digital logic devices must be connected to a high or low bias to prevent them from floating. The logic level that

should be applied to any particular unused input depends on the function of the device. Generally they will be

outputs, unless the part is a transceiver.

12.2 Layout Example

Figure 5. Layout Diagram