Unused Input

Input

Output

Output

Input

Unused Input

–100

–80

–60

–40

–20

0

20

40

60

–1

–0.5 0.0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

4.0

TA = 25°C, VCC = 3 V,

VIH = 3 V, VIL = 0 V,

All Outputs Switching

VOH – V

VOL – V

–20

0

20

40

60

80

100

–0.2

0.0

0.2

0.4

0.6

0.8

1.0

1.2

1.4

1.6

TA = 25°C, VCC = 3 V,

VIH = 3 V, VIL = 0 V,

All Outputs Switching

SN54LVC08A, SN74LVC08A

SCAS283S – JANUARY 1993 – REVISED AUGUST 2015

www.ti.com

Typical Application (continued)

10.2.3 Application Curves

11 Power Supply Recommendations

The power supply can be any voltage between the minimum and maximum supply voltage rating located in

the Recommended Operating Conditions table.

supply, a 0.1-

capacitor is recommended for each power pin. It is ok to parallel multiple bypass capacitors to reject different

frequencies of noise. 0.1-

μF and 1-μF capacitors are commonly used in parallel. The bypass capacitor

should be installed as close to the power pin as possible for best results.

12 Layout

12.1 Layout Guidelines

When using multiple bit logic devices inputs should not ever float. In many cases, functions or parts of

functions of digital logic devices are unused; for example, when only two inputs of a triple-input AND gate are

used or only 3 of the 4 buffer gates are used. Such input pins should not be left unconnected because the

undefined voltages at the outside connections result in undefined operational states. Specified below are the

rules that must be observed under all circumstances. All unused inputs of digital logic devices must be

connected to a high or low bias to prevent them from floating. The logic level that should be applied to any

whichever make more sense or is more convenient.

12.2 Layout Examples

Figure 8. Layout Examples

12

Submit Documentation Feedback

Copyright © 1993–2015, Texas Instruments Incorporated

Product Folder Links: SN54LVC08A SN74LVC08A