TLF9500

November 1994

54F74F219

64-Bit Random Access Memory with TRI-STATE

Outputs

General Description

The ’F219 is a high-speed 64-bit RAM organized as a

16-word by 4-bit array Address inputs are buffered to mini-

mize loading and are fully decoded on-chip The outputs are

TRI-STATE and are in the high-impedance state whenever

the Chip Select (CS) input is HIGH The outputs are active

only in the Read mode This device is similar to the ’F189

but features non-inverting rather than inverting data out-

puts

Features

Y

TRI-STATE outputs for data bus applications

Y

Buffered inputs minimize loading

Y

Address decoding on-chip

Y

Diode clamped inputs minimize ringing

Y

Available in SOIC (300 mil only)

Commercial

Military

Package

Package Description

Number

74F219PC

N16E

16-Lead (0300 Wide) Molded Dual-In-Line

54F219DL (Note 2)

J16A

16-Lead Ceramic Dual-In-Line

74F219SC (Note 1)

M16B

16-Lead (0300 Wide) Molded Small Outline JEDEC

74F219SJ (Note 1)

M16D

16-Lead (0300 Wide) Molded Small Outline EIAJ

54F219FL (Note 2)

W16A

16-Lead Cerpack

54F219LL (Note 2)

E20A

20-Lead Ceramic Leadless Chip Carrier Type C

Note 1

Devices also available in 13

Note 2

Logic Symbol

TLF9500 – 1

Connection Diagrams

Pin Assignment for

DIP SOIC and Flatpak

TLF9500 – 2

Pin Assignment

for LCC

TLF9500 – 3

TRI-STATE

is a registered trademark of National Semiconductor Corporation

C1995 National Semiconductor Corporation

RRD-B30M105Printed in U S A