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VX6854LC 数据表(PDF) 39 Page - STMicroelectronics |
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VX6854LC 数据表(HTML) 39 Page - STMicroelectronics |
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39 / 114 page  DocID027110 Rev 2 39/114 VX6854LC Register map 69 4.14 Data transfer registers [0x0A00 to 0x0A02] 4.15 Shading correction registers [0x0B00 to 0x0B00] Table 25. Data transfer registers [0x0A00 to 0x0A02] Index Byte Register name Data type Default Type Comment 0x0A00 if1_ctrl 8UI 00 RW Bit0: 0 - IF1 transfer disabled 1 - IF1 transfer enabled Bit1: 0 - IF1 read enabled 1 - IF1 write enabled Bit2: 0 - Normal operation 1 - Clear error bits on IF1 0x0A01 if1_status 8UI 00 RW Bit0: Read interface ready Bit1: Write interface ready Bit2: Data corrupt Bit3: Improper interface uage 0x0A02 if1_page_sel 8UI 00 RW Select page for IF1: Page 00: NVM: 0xFC00 - 0xFC3F Page 01: NVM: 0xFC40 - 0xFC7F Page 02: NVM: 0xFC80 - 0xFCBF Page 03: NVM: 0xFCC0 - 0xFCFF Page 04: NVM: 0xFD00 - 0xFD3F Page 05: NVM: 0xFD40 - 0xFD7F Page 06: NVM: 0xFD80 - 0xFDBF Page 07: NVM: 0xFDC0 - 0xFDFF Table 26. Shading correction registers [0x0B00 to 0x0B00] Index Byte Register name Data type Default Type Comment 0x0B00 shading_correction_enable 8UI 01 RW Shading correction 0 - Disable 1 - Enable |
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