54F283DM datasheet(2/10 Pages) NSC

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54F74F

Pin Names

Description

Input IIH IIL

HIGHLOW

Output IOH IOL

A0–A3

A Operand Inputs

1020

20 mA b12 mA

B0–B3

B Operand Inputs

1020

20 mA b12 mA

Carry Input

1010

20 mA b06 mA

S0–S3

Sum Outputs

50333

1 mA20 mA

Carry Output

50333

1 mA20 mA

Functional Description

The ’F283 adds two 4-bit binary words (A plus B) plus the

incoming Carry (C0) The binary sum appears on the Sum

(S0–S3) and outgoing carry (C4) outputs The binary weight

of the various inputs and outputs is indicated by the sub-

script numbers representing powers of two

20 (A0 a B0 a C0) a 21 (A1 a B1)

22 (A2 a B2) a 23 (A3 a B3)

S0 a 2S1 a 4S2 a 8S3 a 16C4

Where (a) e plus

Interchanging inputs of equal weight does not affect the op-

eration Thus C0 A0 B0 can be arbitrarily assigned to pins

5 6 and 7 for DIPS and 7 8 and 9 for chip carrier packages

Due to the symmetry of the binary add function the ’F283

can be used either with all inputs and outputs active HIGH

(positive logic) or with all inputs and outputs active LOW

(negative logic) See

Figure 1 Note that if C0 is not used it

must be tied LOW for active HIGH logic or tied HIGH for

active LOW logic

Due to pin limitations the intermediate carries of the ’F283

are not brought out for use as inputs or outputs However

other means can be used to effectively insert a carry into or

bring a carry out from an intermediate stage

Figure 2

shows how to make a 3-bit adder Tying the operand inputs

of the fourth adder (A3 B3) LOW makes S3 dependent only

on and equal to the carry from the third adder Using some-

what the same principle

Figure 3 shows a way of dividing

the ’F283 into a 2-bit and a 1-bit adder The third stage

adder (A2 B2 S2) is used merely as a means of getting a

carry (C10) signal into the fourth stage (via A2 and B2) and

bringing out the carry from the second stage on S2 Note

that as long as A2 and B2 are the same whether HIGH or

LOW they do not influence S2 Similarly when A2 and B2

are the same the carry into the third stage does not influ-

ence the carry out of the third stage

Figure 4 shows a meth-

od of implementing a 5-input encoder where the inputs are

equally weighted The outputs S0 S1 and S2 present a bina-

ry number equal to the number of inputs I1–I5 that are true

Figure 5 shows one method of implementing a 5-input ma-

jority gate When three or more of the inputs I1–I5 are true

the output M5 is true

Logic Levels

LHLH

Active HIGH

0101

Active LOW

1010

Active HIGH 0 a 10 a 9 e 3 a 16

Active LOW 1 a 5 a 6 e 12 a 0

FIGURE 1 Active HIGH versus Active LOW Interpretation

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