Connection Diagrams

Pin Assignment

for DIP SOIC and Flatpak

TLF9515 – 2

Pin Assignment

for LCC

TLF9515 – 3

Unit LoadingFan Out

54F74F

Pin Names

Description

UL

HIGHLOW

CP

Clock Pulse Input (Active Rising Edge)

1010

Serial Data Input for Right Shift

1010

Serial Data Input for Left Shift

1010

Mode Select Inputs

1020

MR

Asynchronous Master Reset Input (Active LOW)

1010

TRI-STATE Output Enable Inputs (Active LOW)

1010

Parallel Data Inputs or

351083

TRI-STATE Parallel Outputs

15040(333)

b

3 mA24 mA (20 mA)

Serial Outputs

50333

b

1 mA20 mA

Functional Description

The ’F299 contains eight edge-triggered D-type flip-flops

and the interstage logic necessary to perform synchronous

shift left shift right parallel load and hold operations The

the Mode Select Table All flip-flop outputs are brought out

through TRI-STATE buffers to separate IO pins that also

are also brought out on other pins for expansion in serial

shifting of longer words

A LOW signal on MR overrides the Select and CP inputs

and resets the flip-flops All other state changes are initiated

by the rising edge of the clock Inputs can change when the

clock is in either state provided only that the recommended

setup and hold times relative to the rising edge of CP are

observed

STATE buffers and puts the IO pins in the high impedance

state In this condition the shift hold load and reset opera-

tions can still occur The TRI-STATE outputs are also dis-

a parallel load operation

Mode Select Table

Inputs

Response

L

X

X

X

HH

H

HL

H

HH

L

H

L

L

X

Hold

2