Unit LoadingFan Out

54F74F

Pin Names

Description

UL

HIGHLOW

RE

Register Enable Input (Active LOW)

1010

SP

Serial (HIGH) or Parallel (LOW) Mode Control Input

1010

SE

Sign Extend Input (Active LOW)

1030

S

Serial Data Select Input

1020

Serial Data Inputs

1010

CP

Clock Pulse Input (Active Rising Edge)

1010

MR

Asynchronous Master Reset Input (Active LOW)

1010

OE

TRI-STATE Output Enable Input (Active LOW)

1010

Bi-State Serial Output

50333

b

351083

TRI-STATE Parallel Data Outputs

Functional Description

The ’F322 contains eight D-type edge triggered flip-flops

and the interstage gating required to perform right shift and

the intrastage gating necessary for hold and synchronous

parallel load operations A LOW signal on RE enables shift-

ing or parallel loading while a HIGH signal enables the hold

mode A HIGH signal on SP enables shift right while a

LOW signal disables the TRI-STATE output buffers and en-

ables parallel loading In the shift right mode a HIGH signal

mined by the S input A LOW signal on SE enables shift right

function required for the ’F384 Twos Complement Multiplier

A HIGH signal on OE disables the TRI-STATE output buff-

ers regardless of the other control inputs In this condition

the shifting and loading operations can still be performed

Mode Select Table

Mode

Inputs

Outputs

MR

RE

SP

SE

SOE

CP

Clear

L

X

X

X

X

L

X

L

L

L

L

L

L

L

L

L

L

X

X

X

X

H

X

Z

ZZZZZZZ

L

Parallel

HL

L

X

X

X

L

Load

Shift

H

L

H

H

L

L

L

Right

H

L

H

H

H

L

L

Sign

HL

H

L

X

L

L

Extend

Hold

H

H

X

X

X

L

L

NC

NC

NC

NC

NC

NC

NC

NC

NC

Note 1

the IO terminal

Note 2

Note 3

3