Unit LoadingFan Out

54F74F

Pin Names

Description

UL

HIGHLOW

Data Inputs

100667

Data Outputs

50133

b

1 mA8 mA

IR

Input Ready

100667

SI

Shift In

100667

SO

Shift Out

100667

OR

Output Ready

100667

MR

Master Reset

100667

Functional Description

Data Input

puts To enter data the Input Ready (IR) should be HIGH

indicating that the first location is ready to accept data Data

then present at the four data inputs is entered into the first

location when the Shift In (SI) is brought HIGH An SI HIGH

signal causes the IR to go LOW Data remains at the first

location until SI is brought LOW When SI is brought LOW

and the FIFO is not full IR will go HIGH indicating that more

room is available Simultaneously data will propagate to the

second location and continue shifting until it reaches the

output stage or a full location If the memory is full IR will

remain LOW

Data Transfer

Once data is entered into the second cell

the transfer of any full cell to the adjacent (downstream)

empty cell is automatic activated by an on-chip control

Thus data will stack up at the end of the device while empty

fines the time required for the first data to travel from input

to the output of a previously empty device

Data Output

data is shifted to the output stage Output Ready (OR) goes

HIGH indicating the presence of valid data When the OR is

HIGH data may be shifted out by bringing the Shift Out (SO)

HIGH A HIGH signal at SO causes the OR to go LOW Valid

data is maintained while the SO is HIGH When SO is

brought LOW the upstream data provided that stage has

valid data is shifted to the output stage When new valid

data is shifted to the output stage OR goes HIGH If the

before ie data does not change if FIFO is empty

Input Ready and Output Ready

may also be used as

status signals indicating that the FIFO is completely full (In-

Block Diagram

TLF9541 – 4

2