SC2440AEVB datasheet(13/28 Pages) SEMTECH

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Applications Information (Continued)

(2)

where V

CESAT is the switch saturation voltage and VD is volt-

age drop across the freewheeling diode.

For a given output voltage, the switch on time becomes

shorter as V

IN increases. In peak current-mode control, the

PWM modulating ramp is the sensed current ramp of the

power switch.This current ramp is absent unless the switch

is turned on. The switch is turned off when this ramp in-

tersects the error amplifier output. The propagation delay

time required to immediately turn off the switch after it

is turned on is the minimum controllable switch on time

ON(MIN)]. The typical minimum on time is plotted against

temperature in “Typical Characteristics”. t

ON(MIN) increases

with temperature and is also load-dependent. The pow-

er switch in the SC2440A is either not turned on at all or

for at least t

ON(MIN). If the required on time (=

) is shorter

than the minimum on time, the regulator will either jitter

or skip cycles.

Example: Determine the maximum switching frequency

of a dual 2V to .2V and 3.3V regulator. The regulator

needs to work up to 85°C.

We only need to consider the .2V output because this

channel is switching at the lower duty cycle. Assuming

that V

D = 0.45V, VCESAT = 0.3V and VIN = 3.2V (0% high

line), the duty ratio D

of the .2V can be calculated using

equation (2).

To allow for transient headroom and frequency toleranc-

es, the minimum operating switch on time should be at

least 237ns (.3 times the 0.5A minimum on time at 85°C).

The maximum operating frequency of the 2V to .2V and

3.3V converter is therefore

Minimum Off Time Limitation

The PWM latch in Figure 2 is reset every period by the clock.

The clock also turns off the power transistor to refresh the

bootstrap capacitor. This minimum off time limits the at-

tainable duty cycle of the regulator at a given switching

frequency. Measurement shows that the power transistor

is turned off for at least 40ns every switching period to

reset the latch and to refresh the bootstrap capacitor. For

a step-down converter, duty cycle increases with increas-

ing

ratio. If the required duty cycle is higher than the

attainable maximum, then the output voltage will not be

able to reach its set value regardless of the load.

Example: Determine the maximum operating frequency

of a dual 3.3V to .8V and 2.5V switching regulator using

the SC2440A.

The 2.5V channel is switching at the higher duty cycle. As-

suming that V

D = 0.45V, VCESAT = 0.3V and VIN = 2.97V (0%

low line), the duty ratio D

2 of the 2.5V converter can be

calculated using equation (2).

The maximum operating frequency of the .8V and the

2.5V converter is therefore

Transient headroom requires that channel frequency be

set below 380kHz.

External Synchronization

The SC2440A can be synchronized by feeding an external

clock to the SYNC pin. The SYNC input buffer is positive-

edge triggered and TTL-compatible (V

IL < 0.8V and VIH >

2V). The synchronizing frequency can be either X or 2X

the desired channel switching frequency.

1X Frequency Synchronization

If the channels are to be synchronized to run at an exter-

nal clock frequency f

SYNC, then set the free-running chan-

nel frequency between 0.95f

SYNC and fSYNC to allow for

free-running frequency tolerance. The leading edge of

the external clock will lock onto one of the channels and

turn on its power transistor. With X frequency synchroni-

zation, the phase difference between the two channels is

not exactly 80o. However, setting the nominal free-run-

ning channel frequency near f

SYNC will minimize the phase

deviation from 80o.

SC2440A

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