TLF9588

December 1994

54F74F676

16-Bit SerialParallel-In Serial-Out Shift Register

General Description

The ’F676 contains 16 flip-flops with provision for synchro-

nous parallel or serial entry and serial output When the

Mode (M) input is HIGH information present on the parallel

Clock Pulse (CP) input signal When M is LOW data is shift-

ed out of the most significant bit position while information

present on the Serial (SI) input shifts into the least signifi-

cant bit position A HIGH signal on the Chip Select (CS)

input prevents both parallel and serial operations

Features

Y

16-bit parallel-to-serial conversion

Y

16-bit serial-in serial-out

Y

Chip select control

Y

Slim 24 lead 300 mil package

Commercial

Military

Package

Package Description

Number

74F676PC

N24A

24-Lead (0600 Wide) Molded Dual-In-Line

74F676SPC

N24C

24-Lead (0300 Wide) Molded Dual-In-Line

54F676DM (Note 2)

J24A

24-Lead (0600 Wide) Ceramic Dual-In-Line

54F676SDM (Note 2)

J24F

24-Lead (0300 Wide) Ceramic Dual-In-Line

74F676SC (Note 1)

M24B

24-Lead (0300 Wide) Molded Small Outline JEDEC

54F676FM (Note 2)

W24C

24-Lead Cerpack

54F676LM (Note 2)

E28A

24-Lead Ceramic Leadless Chip Carrier Type C

Note 1

Devices also available in 13

Note 2

Connection Diagrams

Pin Assignment

for DIP SOIC and Flatpak

TLF9588 – 2

Pin Assignment

for LCC

TLF9588 – 3

TRI-STATE

is a registered trademark of National Semiconductor Corporation

C1995 National Semiconductor Corporation

RRD-B30M105Printed in U S A