Logic Symbols

TLF9588 – 1

IEEEIEC

TLF9588 – 4

Unit LoadingFan Out

54F74F

Pin Names

Description

UL

HIGHLOW

Parallel Data Inputs

1010

CS

Chip Select Input (Active LOW)

1010

CP

Clock Pulse Input (Active LOW)

1010

M

Mode Select Input

1010

SI

Serial Data Input

1010

SO

Serial Output

50333

b

1 mA20 mA

Functional Description

The 16-bit shift register operates in one of three modes as

indicated in the Shift Register Operations Table

HOLD

a HIGH signal on the Chip Select (CS) input pre-

vents clocking and data is stored in the sixteen registers

ShiftSerial Load

data present on the SI pin shifts into

appearing on the SO pin

Parallel Load

the register on the falling edge of CP The SO output repre-

To prevent false clocking CP must be LOW during a LOW-

to-HIGH transition of CS

Shift Register Operations Table

Control Input

Operating Mode

CS

MCP

H

X

X

Hold

LL

K

ShiftSerial Load

LH

K

Parallel Load

Block Diagram

TLF9588 – 5

2