Data Sheet

3

AEB02800_C

Chopped

Am plifier

Hall

P robe

Latch

Ac tive E rror

Com pensation

Osc illator

&

Sequencer

Threshold

Generator

B ias and

Com pensation

C ircuits

V

S

1

2, 4, 5

GND

Comp arator

w ith

Hysteresis

PRG

6

3

Q

Decision

Logic

Figure 2 Block Diagram

Circuit Description

The Low Power Hall IC Switch comprises a Hall probe, bias generator, compensation

circuits, oscillator, output latch and an n-channel open drain output transistor.

The bias generator provides currents for the Hall probe and the active circuits.

Compensation circuits stabilize the temperature behavior and reduce technology variations.

The Active Error Compensation rejects offsets in signal stages and the influence of

mechanical stress to the Hall probe caused by molding and soldering processes and other

thermal stresses in the package. This chopper technique together with the threshold

generator and the comparator ensures high accurate magnetic switching points.

Very low power consumption is achieved with a timing scheme controlled by an oscillator

and a sequencer. This circuitry activates the sensor for 50 µs (typical operating time) sets

the output state after sequential questioning of the switch points and latches it with the

beginning of the following standby phase (typ. 130 ms). In the standby phase the average

current is reduced to typical 3.5 µA. Because of the long standby time compared to the

operating time the overall averaged current is only slightly higher than the standby current.

By connecting the programming pin to GND (normal to

V

to further reduce the current consumption in applications where a high magnetic field is the