PRELIMINARY

Page 6 of 25

Ref. ISO 7637-1; see test circuit of figure 4 and 5;

∆B

± 0.5V, f

≥ 200Ω;

No.

Parameter

Symbol

Level/typ

Status

1.2.1

Testpulse 1

Testpulse 2

Testpulse 3a

Testpulse 3b

Testpulse 4

Testpulse 5

IV / -100V

IV / 100V

IV / -150V

IV / 100V

IV / -7V

IV / 86.5V

C

2

C

2

A

A

A

C

Note: Test criteria for status A: No missing pulse no additional pulse on the IC output signal plus duty

cycle and jitter are in the specification limits.

Test criteria for status B: No missing pulse no additional pulse on the IC output signal.

(Output signal “OFF” means switching to the voltage of the pull-up resistor).

Test criteria for status C: One or more parameter can be out of specification during the exposure

but returns automatically to normal operation after exposure is removed.

Test criteria for status E: IC destroyed.

Ref. ISO 7637-3; TP 1 and TP 2 ref. DIN 40839-3; see test circuit of figure 4 and 5;

∆B

± 0.5V, f

≥ 200Ω;

No.

Parameter

Symbol

Level/typ

Status

1.2.2

Testpulse 1

Testpulse 2

Testpulse 3a

Testpulse 3b

IV / -30V

IV / 30V

IV / -60V

IV / 40V

A

A

A

A

Ref. ISO 11452-3; see test circuit of figure 4 and 5; measured in TEM-cell;

∆B

± 0,5V, f

≥ 200Ω;

No.

Parameter

Symbol

Level/max

Remarks

1.2.3

EMC field strength

IV / 200V/m

AM=80%, f=1kHz;

Note: Stresses above those listed here may cause permanent damage to the device. Exposure to

absolute maximum rating conditions for extended periods may affect device reliability.

±200mV and

horizontal limits are

±200µs.