TLF9581

December 1994

54F74F651

TransceiversRegisters

General Description

These devices consist of bus transceiver circuits with

D-type flip-flops and control circuitry arranged for multi-

plexed transmission of data directly from the input bus or

from internal registers Data on the A or B bus will be

clocked into the registers as the appropriate clock pin goes

to HIGH logic level Output Enable pins (OEAB OEBA) are

provided to control the transceiver function

Features

Y

Independent registers for A and B buses

Y

Multiplexed real-time and stored data

Y

Choice of non-inverting and inverting data paths

’F651 inverting

’F652 non-inverting

Y

Guaranteed 4000V minimum ESD protection

Commercial

Military

Package

Package Description

Number

74F651SPC

N24C

24-Lead (0300 Wide) Molded Dual-In-Line

54F651SDM (Note 2)

J24F

24-Lead (0300 Wide) Ceramic Dual-In-Line

74F651SC (Note 1)

M24B

24-Lead (0300 Wide) Molded Small Outline JEDEC

54F651FM (Note 2)

W24C

24-Lead Cerpack

54F651LM (Note 2)

E28A

24-Lead Ceramic Leadless Chip Carrier Type C

74F652SPC

N24C

24-Lead (0300 Wide) Molded Dual-In-Line

54F652SDM (Note 2)

J24F

24-Lead (0300 Wide) Ceramic Dual-In-Line

74F652SC (Note 1)

M24B

24-Lead (0300 Wide) Molded Small Outline JEDEC

54F652FM (Note 2)

W24C

24-Lead Cerpack

54F652LM (Note 2)

E28A

24-Lead Ceramic Leadless Chip Carrier Type C

Note 1

Devices also available in 13

Note 2

Connection Diagrams

Pin Assignment

DIP SOIC and Flatpak

TLF9581 – 3

Pin Assignment

for LCC

TLF9581 – 4

TRI-STATE

is a registered trademark of National Semiconductor Corporation

C1995 National Semiconductor Corporation

RRD-B30M75Printed in U S A