ESS Technology, Inc.

SAM0377-052101

3

ES4318 PRODUCT BRIEF

TDMDX

25

O

TDM transmit data.

RSEL

I

ROM Select

TDMDR

28

I

TDM receive data.

TDMCLK

29

I

TDM clock input.

TDMFS

30

I

TDM frame synch.

TDMTSC#

31

O

TDM output enable, active low.

TWS

32

O

Audio transmit frame sync.

SEL_PLL1

I

Select PLL1.

TSD

33

O

Audio transmit serial data port.

SEL_PLL0

I

Select PLL0.

SEL_PLL2

36

Select PLL2. See the table for pin number 33.

MCLK

39

I/O

Audio master clock for audio DAC.

TBCK

40

I/O

Audio transmit bit clock.

SPDIF_DOBM

41

O

S/PDIF (IEC958) Format Output.

RSD

45

I

Audio receive serial data.

RWS

46

I

Audio receive frame synch.

RBCK

47

I

Audio receive bit clock.

APLLCAP

48

I

Analog PLL Capacitor.

XIN

49

I

Crystal input.

XOUT

50

O

Crystal output.

DMA[11:0]

66:61,58:53

O

DRAM address bus.

DCAS#

69

O

Column address strobe, active low.

DOE#

70

O

Output enable, active low.

DSCK_EN

I

Clock Enable, active low.

DWE#

71

O

DRAM write enable, active low.

DRAS[2:0]#

74:72

O

Row address strobe, active low.

DB[15:0]

96:93,90:85,82:77

I/O

DRAM data bus.

DCS[1:0]#

97,100

O

SDRAM chip select [1:0], active low.

DQM

101

O

Data input/output mask.

DSCK

102

O

Clock to SDRAM.

DCLK

105

I

Clock Input (27 MHz)

YUV[7:0]

115:113,110:106

O

8-bit YUV output.

PCLK2XSCN

116

I/O

2X pixel clock.

PCLKQSCN

117

I/O

Pixel clock.

VSYNCH#

118

I/O

Vertical sync for screen video interface, programmable for rising or falling edge, active low.

HSYNCH#

119

I/O

Horizontal sync for screen video interface, programmable for rising or falling edge, active low.

HD[15:0]

141:140,137:131,128:122

O

Host data bus

HCS1FX#

152

O

Host select 1.

HCS3FX#

153

O

Host select 3.

HIOCS16#

151

I

Device 16-bit data transfer.

HA[2:0]

158, 155:154

I/O

Host address bus.

VPP

159

I

Peripheral protection voltage.

HWR#/DCI_ACK#

149

I,I

Host write/DCI Interface Acknowledge Signal, active low.

HRD#/DCI_CLK

150

I,I

Host read/DCI Interface Clock.

HD[15:0]

141:140,137:131,128:122

I/O

Host data bus.

HWRQ#

142

O

Host write request.

HRDQ#

143

O

Host read request.

HIRQ

144

I/O

Host interrupt.

HRST#

145

O

Host reset.

HIORDY

146

I

Host I/O ready.

HWR#

149

O

Host write request.

AUX[7:0]

169:165,162:160

I/O

Auxiliary ports.

LOE#

170

O

Device output enable, active low.

LCS[3:0]#

176:173

O

Chip select [3:0], active low.

LD[15:0]

197:194, 191:185, 182:178

I/O

Device data bus.

LWRLL#

198

O

Device write enable, active low.

LWRHL#

199

O

Device write enable, active low.

NC

37,38,42,203:202

No connect.

Name

Number

I/O

Definition

RSEL

Selection

016-bit ROM

1

8-bit ROM

SEL_PLL2

SEL_PLL0

Clock Output

0

0

2.5 x DCLK

01

3 x DCLK

1

0

3.5 x DCLK

11

4 x DCLK