Functional Description

The ’F825 consists of eight D-type edge-triggered flip-flops

This device has TRI-STATE true outputs and is organized in

broadside pinning In addition to the clock and output en-

able pins the buffered clock (CP) and buffered Output En-

able (OE) are common to all flip-flops The flip-flops will

store the state of their individual D inputs that meet the

setup and hold times requirements on the LOW-to-HIGH CP

transition With the OE LOW the contents of the flip-flops

are available at the outputs When the OE is HIGH the out-

puts go to the high impedance state Operation of the OE

input does not affect the state of the flip-flops The ’F825

has Clear (CLR) and Clock Enable (EN) pins

When the CLR is LOW and the OE is LOW the outputs are

LOW When CLR is HIGH data can be entered into the flip-

flops When EN is LOW data on the inputs is transferred to

the outputs on the LOW-to-HIGH clock transition When the

EN is HIGH the outputs do not change state regardless of

the data or clock input transitions

Function Table

Inputs

Internal

Output

Function

OE

CLR

EN

CP

D

Q

O

H

H

L

H

X

NC

Z

Hold

H

H

L

L

X

NC

Z

Hold

H

H

H

X

X

NC

Z

Hold

L

H

H

X

X

NC

NC

Hold

H

L

X

X

X

H

Z

Clear

L

L

X

X

X

H

L

Clear

HH

L

L

L

H

Z

Load

HH

L

L

H

L

Z

Load

LH

L

L

L

H

L

Data Available

LH

L

L

H

L

H

Data Available

L

H

L

H

X

NC

NC

No Change in Data

L

H

L

L

X

NC

NC

No Change in Data

Logic Diagram

TLF9597 – 5

Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays

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