RT9202CS datasheet(13/16 Pages) RICHTEK

13 / 16 page

RT9202

DS9202-02 August 2002

www.richtek.com

Fig. 9

PWM Layout Considerations

MOSFETs switch very fast and efficiently. The speed

with which the current transitions from one device to

another

causes

voltage

spikes

across

the

interconnecting impedances and parasitic circuit

elements. The voltage spikes can degrade efficiency

and radiate noise, that results in ocer-voltage stress

on devices. Careful component placement layout and

printed circuit design can minimize the voltage spikes

induced in the converter. Consider, as an example,

the turn-off transition of the upper MOSFET prior to

turn-off, the upper MOSFET was carrying the full load

current. During turn-off, current stops flowing in the

upper MOSFET and is picked up by the low side

MOSFET or Schottky diode. Any inductance in the

switched current path generates a large voltage spike

during the switching interval. Careful component

selections, layout of the critical components, and use

shorter and wider PCB traces help in minimizing the

magnitude of voltage spikes.

There are two sets of critical components in a DC-DC

converter using the RT9202. The switching power

components are most critical because they switch

large amounts of energy, and as such, they tend to

generate equally large amounts of noise. The critical

small signal components are those connected to

sensitive nodes or those supplying critical bypass

current.

The power components and the PWM controller

should be placed firstly. Place the input capacitors,

especially the high-frequency ceramic decoupling

capacitors, close to the power switches. Place the

output inductor and output capacitors between the

MOSFETs and the load. Also locate the PWM

controller near by MOSFETs.

A multi-layer printed circuit board is recommended.

Fig.10

shows

the

connections

the

critical

components in the converter. Note that the capacitors

CIN and COUT each of them represents numerous

physical capacitors. Use a dedicated grounding plane

and use vias to ground all critical components to this

layer. Apply another solid layer as a power plane and

cut this plane into smaller islands of common voltage

levels. The power plane should support the input

power and output power nodes. Use copper filled

polygons on the top and bottom circuit layers for the

PHASE node, but it is not necessary to oversize this

particular island. Since the PHASE node is subjected

to very high dV/dt voltages, the stray capacitance

formed between these island and the surrounding

circuitry will tend to couple switching noise. Use the

remaining printed circuit layers for small signal

routing. The PCB traces between the PWM controller

and the gate of MOSFET and also the traces

connecting source of MOSFETs should be sized to

carry 2A peak currents.

Fig. 10

LOAD

RT9202

VCC

GND

LGATE

UGATE

VOUT

IQ1

IQ2

GND

VIN

COUT

VOUT

RT9202

< 1K

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