| 数据搜索系统,热门电子元器件搜索 |
|
ICS1524 数据表(PDF) 21 Page - Integrated Circuit Systems |
|
|
|||||||||||||||||||||||||||||
ICS1524 数据表(HTML) 21 Page - Integrated Circuit Systems |
|
21 / 24 page ![]() 21 ICS1524 ICS1524 Rev C 01/31/2003 l o b m y Sn o i t p i r c s e D g n i m i Tn i Mp y Tx a Ms t i n U t0 y a l e d F E R o t C N Y S H3 . 1 15 . 1 12 1s n t1 y a l e d k c o l c L C E P o t F E R0 . 1 -8 . 02 . 2s n t2 t , 3 e l c y c y t u d k c o l c L C E P5 40 55 5% t4 y a l e d k c o l c 3 _ L T S S o t k c o l c L C E P2 . 05 7 . 02 . 1s n t5 y a l e d T U O _ C N U F o t k c o l c L C E P5 . 19 . 13 . 2s n t6 k c o l c 2 / L C E P o t k c o l c L C E P0 . 13 . 15 . 1s n t7 y a l e d 2 / K L C – 3 _ L T S S o t k c o l c L C E P1 . 14 . 18 . 1s n t8 t , 9 e l c y c y t u d k c o l c L T S S5 40 55 5% *Note: Measured at 3.6V 0°C, 135-MHz output frequency, PECL clock lines to 75 Οηµ termination, SSTL_3 clock lines unterminated, 20-pF load. Transition times vary based on termination. Typical Transition Times* Output Timing* REF HSYNC PECL CLK- PECL CLK+ SSTL-CLK FUNC_OUT t0 tR tS tF t5 t4 t8 t9 t1 t2 t3 tp PECL DPACLK- PECL DPACLK+ SSTL-DPACLK FUNC t DPA t8 t9 tS tF t4 t1 t2 t3 tp l o b m y Sn o i t p i r c s e D g n i m i Te s i Rll a Fs t i n U tR F E R8 . 28 . 1s n tP K L C L C E P0 . 12 . 1s n tS K L C - L T S S6 . 17 . 0s n tF T U O _ C N U F2 . 10 . 1s n |
|
|
链接网址 |
| ALLDATASHEET是否为您带来帮助? [ DONATE ] |
关于 Alldatasheet | 广告服务 | 联系我们 | 隐私政策 | 数据表链接 | 链接交换 | 制造商名单 All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |