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Semicustom Products

UT90nHBD Hardened-by-Design (HBD)

Standard Cell

Preliminary Data Sheet

August 2014

www.aeroflex.com/RadHardASIC

FEATURES

 Up to 50,000,000 2-input NAND equivalent gates with

a 1.0V Core using standard cell architecture

 Toggle rates up to 5.0 GHz

 Advanced 90nm silicon gate CMOS processed in a com-

mercial fab

 Operating voltages: 2.5V and 1.8V I/O; 1.0V core

 Radiation hardened from 100 krads(Si) to 1 Mrads(Si)

total dose available

 Comprehensive set of core standard cells with multiple

 Design support for Mentor Graphics®, Synopsys®,

Linux workstations

 Power dissipation of 7nW/MHz/gate at V

and 20% duty cycle

 External chip capacitor attachment option available to

space quality levels (for improved SSO response)

 UT90nHBD ASIC technology is available under Aero-

flex’s Accreditation of Trust Category 1A from design

through device qualification and delivery.

 QML Class Y non-hermetic Flip Chip ceramic

packaging

 Standard Microelectronics Drawing - 5962-14B01

PRODUCT DESCRIPTION

The high-performance UT90nHBD Hardened-by-Design

ASIC standard cell family features densities up to, and be-

yond 50,000,000 equivalent NAND2 gates.

The deep submicron ASIC family uses a highly efficient

standard cell architecture for the internal cell instantiation.

Combined with state-of-the-art place and route tools, the

area utilization and signal interconnect of transistors is max-

imized using eight levels of copper metal interconnect.

Extensive Cell Library

The UT90nHBD standard cell family is supported by an

extensive cell library with over 900 elements. User select-

able options for cell configurations include scan for all

register elements, output drive strengths (1x to 30x) and

UT90nHBD Design Manual for complete cell listing and

details.

Aeroflex Gaisler IP

We offer Aeroflex Gaisler Processor IP. A complete library

of Aeroflex Gaisler IP can be reviewed at www.Aero-

flex.com/Gaisler.