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AX88796L 数据表(PDF) 5 Page - ASIX Electronics Corporation |
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AX88796L 数据表(HTML) 5 Page - ASIX Electronics Corporation |
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5 / 71 page ![]() ASIX ELECTRONICS CORPORATION 5 AX88796 L 3-in-1 Local Bus Fast Ethernet Controller 1.0 Introduction 1.1 General Description: The AX88796 provides industrial standard NE2000 registers level compatible instruction set. Various drivers are easy acquired, maintenance and usage. No much additional effort to be paid. Software is easily port to various embedded systems with no pain and tears The AX88796 Fast Ethernet Controller is a high performance and highly integrated local CPU bus Ethernet Controller with embedded 10/100Mbps PHY/Transceiver and 8K*16 bit SRAM. The AX88796 supports both 8 bit and 16 bit local CPU interfaces include MCS-51 series, 80186 series, MC68K series CPU and ISA bus. The AX88796 implements both 10Mbps and 100Mbps Ethernet function based on IEEE802.3 / IEEE802.3u LAN standard. The AX88796 also provides an extra IEEE802.3u compliant media-independent interface (MII) to support other media applications. Using MII interface, Home LAN PHY type media can be supported. As well as, the chip also provides optional Standard Print Port ( parallel port interface ), can be used for printer server device or treat as simple general I/O port. The chip also support upto 3/1 additional General Purpose In/Out pins The main difference between AX88796 and AX88195 are : 1) Embedded packet buffer memory 2) Built-in 10/100Mbps PHY/Transceiver 3) Replace memory I/F with PHY/Transceiver I/F. 4) Canceling SAX address decoding. 5) Fix interrupt status can’t always clean up problem of AX88195. 6) Add upto 3/1 general Purpose In/Out pins. AX88796 use 128-pin LQFP low profile package, 25MHz operation, and single 3.3V operation with 5V I/O tolerance. The ultra low power consumption is an outstanding feature and enlarges the application field. It is suitable for some power consumption sensitive product like small size embedded products, PDA (Personal Digital Assistant) and Palm size computer …etc. 1.2 AX88796 Block Diagram: Fig - 1 AX88796 Block Diagram MAC Core & PHY+ Tranceiver 8K* 16 SRAM and Memory Arbiter Remote DMA FIFOs NE2000 Registers Host Interface STA SEEPROM I/F SD[15:0] SA[9:0] Ctl BUS MII I/F EECS EECK EEDI EEDO TPI, TPO SPP / GPIO Print Port or General I/O SMDC SMDIO |
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