TLF5952

February 1988

CD4019BMCD4019BC Quad AND-OR Select Gate

General Description

The CD4019BMCD4019BC is a complementary MOS quad

AND-OR select gate Low power and high noise margin

over a wide voltage range is possible through implementa-

tion of N- and P-channel enhancement mode transistors

These complementary MOS (CMOS) transistors provide the

building blocks for the 4 ‘‘AND-OR select’’ gate configura-

tions each consisting of two 2-input AND gates driving a

single 2-input OR gate Selection is accomplished by control

charge damage

Features

Y

Wide supply voltage range

30V to 15V

Y

High noise immunity

Y

Low power TTL

Fan out of 2 driving 74L

compatibility

or 1 driving 74LS

Applications

Y

AND-OR select gating

Y

Shift-rightshift-left registers

Y

Truecomplement selection

Y

ANDOREXCLUSIVE-OR selection

Connection and Schematic Diagrams

Dual-In-Line Package

TLF5952 – 1

Top View

Order Number CD4019B

TLF5952 – 2

Schematic diagram for 1 of 4 identical stages

C1995 National Semiconductor Corporation

RRD-B30M105Printed in U S A