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CD4046BC 数据表(PDF) 11 Page - National Semiconductor (TI) |
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CD4046BC 数据表(HTML) 11 Page - National Semiconductor (TI) |
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11 / 14 page ![]() Design Information This information is a guide for approximating the value of external components for the CD4046B in a phase-locked- loop system The selected external components must be within the following ranges R1 R2 t 10 kX RS t 10 kX C1 t 50 pF In addition to the given design information refer to Figure 5 for R1 R2 and C1 component selections Using Phase Comparator I Using Phase Comparator II Characteristics VCO Without Offset VCO With Offset VCO Without Offset VCO With Offset R2 e % R2 e % VCO Frequency For No Signal Input VCO in PLL system will adjust VCO in PLL system will adjust to to center frequency fo lowest operating frequency fmin Frequency Lock 2 fL e full VCO frequency range Range 2 fL 2fL e fmax b fmin Frequency Capture Range 2 fC 2fC 1 q 02 q fL u1 Loop Filter fC e fL Component Selection For 2 fC see Ref Phase Angle Between 90 at center frequency (fo) approximating Always 0 in lock Single and Comparator 0 and 180 at ends of lock range (2 fL) Locks on Harmonics Yes No of Center Frequency Signal Input Noise High Low Rejection VCO Component Given fo Given fo and fL Given fmax Given fmin and fmax Selection Use fo with Calculate fmin Calculate fo from Use fmin with Figure 5a to from the equation the equation Figure 5b to determine R1 determine R2 and C1 fmin e fo b fL and C1 fo e fmax 2 Use fmin with Figure 5b Calculate fmax fmin to determine R2 and C1 Use fo with Figure 5a to determine R1 and C1 Use fmax fmin with Figure 5c Calculate fmax fmin to determine ratio from the equation R2R1 to obtain R1 fmax fmin e fo a fL fo b fL Use fmax fmin with Figure 5c to determine ratio R2 R1 to obtain R1 TLF5968 – 7 TLF5968 – 9 TLF5968 – 10 TLF5968 – 8 TLF5968 – 11 TLF5968 – 12 References GS Moschytz ‘‘Miniaturized RC Filters Using Phase-Locked Loop’’ BSTJ May 1965 Floyd Gardner ‘‘Phaselock Techniques’’ John Wiley Sons 1966 11 |
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