2–1

2 Functional Description

2.1

MCU Memory Map

Figure 2–1 illustrates the MCU memory map under boot and normal operation. It must be noted that the internal 256

bytes of IDATA are not shown since it is assumed to be in the standard 8052 location (0000 to 00FF). The shaded

areas represent the internal ROM/RAM.

When SDW bit = 0 (Boot mode): The 6k-ROM is mapped to address (0000–17FF) and is duplicated in location

(8000–97FF) in code space. The internal 8k-RAM is mapped to address range (0000–1FFF) in data space. Buffers,

MMR and I/O are mapped to address range (FD80–FFFF) in data space.

When SDW bit = 1 (Normal mode): The 6k-ROM is mapped to (8000–97FF) in code space. The internal 8k-RAM

is mapped to address range (0000–1FFF) code space. Buffers, MMR and I/O are mapped to address range

(FD80–FFFF) in data space.

Boot Mode (SDW = 0)

Normal Mode (SDW = 1)

CODE

XDATA

CODE

XDATA

0000

6k Boot ROM

6k Boot ROM

8k

8k

17FF

8k

RAM

8k

Code RAM

RAM

Read/Write

Code RAM

Read Only

1FFF

8000

6k Boot ROM

6k Boot ROM

6k Boot ROM

6k Boot ROM

97FF

FD80

512 Bytes

512 Bytes

512 Bytes

RAM

512 Bytes

RAM

FF80

MMR

MMR

FFFF

MMR

MMR

Figure 2–1. MCU Memory Map (TUSB3210)