XRT72L13 datasheet(76/370 Pages) EXAR

76 / 370 page

XRT72L13

MULTIPLEXER/FRAMER IC

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PRELIMINARY

REV. 1.0.6

TABLE 1: DESCRIPTION OF THE MICROPROCESSOR INTERFACE SIGNALS THAT EXHIBIT CONSTANT ROLES IN BOTH

THE

"INTEL" AND "MOTOROLA" MODES

PIN NAME

TYPE

DESCRIPTION

MOTO

Selection input for Intel/Motorola µP Interface.

Setting this pin to a logic "high" configures the Microprocessor Interface to operate in the "Motor-

ola" mode. Likewise, setting this pin to a logic "low" configures the Microprocessor Interface to

operate in the "Intel" Mode.

D[7:0]

I/O

Bi-Directional Data Bus for register read or write operations

A[8:0]

Nine Bit Address Bus input:

This nine bit Address Bus is provided to allow the user to select an on-chip register or on-chip RAM

location.

CSB

Chip Select input. This "active low" signal selects the Microprocessor Interface of the UNI device

and enables read/write operations with the on-chip registers/on-chip RAM.

IntB

Interrupt Request Output: This "open-drain/active-low" output signal will inform the local

µP that

the UNI has an interrupt condition that needs servicing.

TABLE 2: PIN DESCRIPTION OF MICROPROCESSOR INTERFACE SIGNALS - WHILE THE MICROPROCESSOR INTERFACE

OPERATING IN THE INTEL MODE

PIN NAME

EQUIVALENT PIN

INTEL

ENVIRONMENT

TYPE

DESCRIPTION

ALE_AS

ALE

Address-Latch Enable: This "active-high" signal is used to latch the contents on

the address bus, A[8:0]. The contents of the Address Bus are latched into the

A[8:0] inputs on the falling edge of ALE_AS. Additionally, this signal can be used

to indicate the start of a burst cycle.

RdB_DS

RD*

Read Signal: This "active-low" input functions as the read signal from the local

µP. When this signal goes "low", the UNI Microprocessor Interface will place the

contents of the addressed register on the Data Bus pins (D[15:0]). The Data

Bus will be "tri-stated" once this input signal returns "high".

WRB_RW

WR*

Write Signal: This "active-low" input functions as the write signal from the local

µP. The contents of the Data Bus (D[15:0]) will be written into the addressed reg-

ister (via A[8:0]), on the rising edge of this signal.

Rdy_Dtck

READY*

Ready Output: This "active-low" signal is provided by the UNI device, and indi-

cates that the current read or write cycle is to be extended until this signal is

asserted. The local

µP will typically insert "WAIT" states until this signal is

asserted. This output will toggle "low" when the device is ready for the next Read

or Write cycle.

XRT72L13 数据表(PDF) 76 Page - Exar Corporation

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