TLF6368

June 1989

54LS109DM54LS109ADM74LS109A

Dual Positive-Edge-Triggered J-K Flip-Flops

with Preset Clear and Complementary Outputs

General Description

This device contains two independent positive-edge-trig-

gered J-K flip-flops with complementary outputs The J and

K data is accepted by the flip-flop on the rising edge of the

clock pulse The triggering occurs at a voltage level and is

not directly related to the transition time of the rising edge of

the clock The data on the J and K inputs may be changed

while the clock is high or low as long as setup and hold

times are not violated A low logic level on the preset or

clear inputs will set or reset the outputs regardless of the

logic levels of the other inputs

Features

Y

Alternate MilitaryAerospace device (54LS109) is avail-

able Contact a National Semiconductor Sales Office

Distributor for specifications

Connection Diagram

Dual-In-Line Package

TLF6368 – 1

Order Number 54LS109DMQB 54LS109FMQB DM54LS109AJ

DM54LS109AW DM74LS109AM or DM74LS109AN

See NS Package Number J16A M16A N16E or W16A

Function Table

Inputs

Outputs

PR

CLR

CLK

J

K

QQ

LH

X

X

X

H

L

HL

X

X

X

L

H

LL

X

X

X

H

H

HH

u

LL

L

H

HH

u

H

L

Toggle

HH

u

LH

HH

u

HH

H

L

HH

L

X

X

e

This configuration is nonstable that is it will not persist when preset

andor clear inputs return to their inactive (high) state

established

each active transition of the clock pulse

C1995 National Semiconductor Corporation

RRD-B30M105Printed in U S A