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SWCS049 数据表(PDF) 93 Page - Texas Instruments |
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SWCS049 数据表(HTML) 93 Page - Texas Instruments |
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93 / 119 page  93 TPS659110, TPS659112, TPS659113 TPS659114, TPS659118, TPS6591133 www.ti.com SWCS049Q – JUNE 2010 – REVISED MARCH 2016 Submit Documentation Feedback Product Folder Links: TPS659110 TPS659112 TPS659113 TPS659114 TPS659118 TPS6591133 Detailed Description Copyright © 2010–2016, Texas Instruments Incorporated Bits Field Name Description Type Reset 1 VMBHI_IT_MSK VBAT > VMBHI interrupt event mask bit When 0, interrupt not masked. Device automatically switches on at NO SUPPLY-to-OFF BACKUP-to-OFF transition When 1, interrupt is masked. Device does not switch on until a start reason is received. (EEPROM bit. Default value: See boot configuration) RW 1 0 PWRHOLD_F_IT_MS K PWRHOLD falling-edge event interrupt mask. RW 1 Table 6-68. INT_STS2_REG Address Offset 0x52 Physical Address Instance (RESET DOMAIN: FULL RESET) Description Interrupt status register: The interrupt status bit is set to 1 when the associated interrupt event is detected. Interrupt status bit is cleared by writing 1. Type RW 7 6 5 4 3 2 1 0 GPIO3_F_IT GPIO3_R_IT GPIO2_F_IT GPIO2_R_IT GPIO1_F_IT GPIO1_R_IT GPIO0_F_IT GPIO0_R_IT Bits Field Name Description Type Reset 7 GPIO3_F_IT GPIO3 falling-edge detection interrupt status RW W1 to Clr 0 6 GPIO3_R_IT GPIO3 rising-edge detection interrupt status RW W1 to Clr 0 5 GPIO2_F_IT GPIO2 falling-edge detection interrupt status RW W1 to Clr 0 4 GPIO2_R_IT GPIO2 rising-edge detection interrupt status RW W1 to Clr 0 3 GPIO1_F_IT GPIO1 falling-edge detection interrupt status RW W1 to Clr 0 2 GPIO1_R_IT GPIO1 rising-edge detection interrupt status RW W1 to Clr 0 1 GPIO0_F_IT GPIO0 falling-edge detection interrupt status RW W1 to Clr 0 0 GPIO0_R_IT GPIO0 rising-edge detection interrupt status RW W1 to Clr 0 Table 6-69. INT_MSK2_REG Address Offset 0x53 Physical Address Instance (RESET DOMAIN: GENERAL RESET) Description Interrupt mask register: When *_IT_MSK is set to 1, the associated interrupt is masked: INT1 signal is not activated, but *_IT interrupt status bit is updated. When *_IT_MSK is set to 0, the associated interrupt is enabled: INT1 signal is activated, *_IT is updated. Type RW 7 6 5 4 3 2 1 0 GPIO3_F_ IT_MSK GPIO3_R_ IT_MSK GPIO2_F_ IT_MSK GPIO2_R_ IT_MSK GPIO1_F_ IT_MSK GPIO1_R_ IT_MSK GPIO0_F_ IT_MSK GPIO0_R_ IT_MSK |
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