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SWCS049A 数据表(PDF) 89 Page - Texas Instruments |
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SWCS049A 数据表(HTML) 89 Page - Texas Instruments |
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89 / 119 page  89 TPS659110, TPS659112, TPS659113 TPS659114, TPS659118, TPS6591133 www.ti.com SWCS049Q – JUNE 2010 – REVISED MARCH 2016 Submit Documentation Feedback Product Folder Links: TPS659110 TPS659112 TPS659113 TPS659114 TPS659118 TPS6591133 Detailed Description Copyright © 2010–2016, Texas Instruments Incorporated Table 6-62. EN1_LDO_ASS_REG (continued) Description Configuration Register setting the LDO regulators, driven by the multiplexed SCLSR_EN1 signal. When control bit = 1, LDO regulator state is driven by the SCLSR_EN1 control signal and is also defined though SLEEP_KEEP_LDO_ON register setting: When SCLSR_EN1 is high the regulator is on, When SCLSR_EN1 is low: - the regulator is off if its corresponding Control bit = 0 in SLEEP_KEEP_LDO_ON register - the regulator is working in low-power mode if its corresponding control bit = 1 in SLEEP_KEEP_LDO_ON register When control bit = 0 no effect: LDO regulator state is driven though registers programming and the device state Any control bit of this register set to 1 will disable the I2C SR Interface functionality Type RW 7 6 5 4 3 2 1 0 LDO3_EN1 LDO4_EN1 LDO7_EN1 LDO8_EN1 LDO5_EN1 LDO2_EN1 LDO1_EN1 LDO6_EN1 Bits Field Name Description Type Reset 7 LDO3_EN1 Setting supply state control though SCLSR_EN1 signal RW 0 6 LDO4_EN1 Setting supply state control though SCLSR_EN1 signal RW 0 5 LDO7_EN1 Setting supply state control though SCLSR_EN1 signal RW 0 4 LDO8_EN1 Setting supply state control though SCLSR_EN1 signal RW 0 3 LDO5_EN1 Setting supply state control though SCLSR_EN1 signal RW 0 2 LDO2_EN1 Setting supply state control though SCLSR_EN1 signal RW 0 1 LDO1_EN1 Setting supply state control though SCLSR_EN1 signal RW 0 0 LDO6_EN1 Setting supply state control though SCLSR_EN1 signal RW 0 Table 6-63. EN1_SMPS_ASS_REG Address Offset 0x46 Physical Address Instance (RESET DOMAIN: TURNOFF RESET) Description Configuration Register setting the SMPS Supplies driven by the multiplexed SCLSR_EN1 signal. When control bit = 1, SMPS Supply state and voltage is driven by the SCLSR_EN1 control signal and is also defined though SLEEP_KEEP_RES_ON register setting. When control bit = 0 no effect: SMPS Supply state is driven though registers programming and the device state. Any control bit of this register set to 1 will disable the I2C SR Interface functionality Type RW 7 6 5 4 3 2 1 0 Reserved SPARE_EN1 VDDCTRL_ EN1 VDD2_EN1 VDD1_EN1 VIO_EN1 Bits Field Name Description Type Reset 7:5 Reserved RO R returns 0s 0x0 4 SPARE_EN1 Spare bit RW 0 3 VDDCTRL_EN1 When control bit = 1: When EN1 is high the supply voltage is programmed though VDDCtrl_OP_REG register, and it can also be programmed off. When EN1 is low the supply voltage is programmed though VDDCtrl_SR_REG register, and it can also be programmed off. When control bit = 0: No effect: Supply state is driven though registers programming and the device state RW 0 |
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