TLF6373

June 1989

54LS74DM54LS74ADM74LS74A

Dual Positive-Edge-Triggered D Flip-Flops

with Preset Clear and Complementary Outputs

General Description

This device contains two independent positive-edge-trig-

gered D flip-flops with complementary outputs The informa-

tion on the D input is accepted by the flip-flops on the posi-

tive going edge of the clock pulse The triggering occurs at a

voltage level and is not directly related to the transition time

of the rising edge of the clock The data on the D input may

be changed while the clock is low or high without affecting

the outputs as long as the data setup and hold times are not

violated A low logic level on the preset or clear inputs will

set or reset the outputs regardless of the logic levels of the

other inputs

Features

Y

Alternate militaryaerospace device (54LS74) is avail-

able Contact a National Semiconductor Sales Office

Distributor for specifications

Connection Diagram

Dual-In-Line Package

TLF6373 – 1

Order Number 54LS74DMQB 54LS74FMQB 54LS74LMQB

DM54LS74AJ DM54LS74AW DM74LS74AM or DM74LS74AN

See NS Package Number E20A J14A M14A N14A or W14B

Function Table

Inputs

Outputs

PR

CLR

CLK

D

Q

Q

LH

X

X

H

L

HL

X

X

L

H

LL

X

X

H

H

HH

u

HH

L

HH

u

LL

H

HH

L

X

e

This configuration is nonstable that is it will not persist when either the preset

andor clear inputs return to their inactive (high) level

C1995 National Semiconductor Corporation

RRD-B30M105Printed in U S A