SP503 datasheet(8/29 Pages) SIPEX

8 / 29 page

Date: 7/29/04

SP503 Multiprotocol Transceiver

Pin 32 — V

SS –10V Charge Pump Capacitor —

Connects from ground to V

SS.

Suggested ca-

pacitor size is 22

µF, 16V.

Pins 26 and 30 — C

+ and C

– — Charge Pump

Capacitor — Connects from C

+ to C

–. Sug-

gested capacitor size is 22

µF, 16V.

Pins 28 and 31 — C

+ and C

– — Charge Pump

Capacitor — Connects from C

+ to C

–. Sug-

gested capacitor size is 22

µF, 16V.

NOTE: NC pins should be left floating; internal

signals may be present.

pared to older less–efficient designs. The charge

pump still requires four external capacitors, but

uses a four–phase voltage shifting technique to

attain symmetrical 10V power supplies. Figure

3(a) shows the waveform found on the positive

side of capcitor C2, and Figure 3(b) shows the

negative side of capcitor C2. There is a free–

running oscillator that controls the four phases

of the voltage shifting. A description of each

phase follows.

Phase 1

— V

SS charge storage —During this phase of

the clock cycle, the positive side of capacitors

1 and C2 are initially charged to +5V. Cl

+ is

then switched to ground and the charge on C

– is

transferred to C

–. Since C

+ is connected to

+5V, the voltage potential across capacitor C

is now 10V.

Phase 2

— V

SS transfer — Phase two of the clock con-

nects the negative terminal of C

2 to the VSS

storage capacitor and the positive terminal of C

to ground, and transfers the generated –l0V to

3. Simultaneously, the positive side of capaci-

tor C

1 is switched to +5V and the negative side

is connected to ground.

Phase 3

— V

DD charge storage — The third phase of the

clock is identical to the first phase — the charge

transferred in C

1 produces –5V in the negative

terminal of C

1, which is applied to the negative

side of capacitor C

2. Since C2

+ is at +5V, the

voltage potential across C

2 is l0V.

Phase 4

— V

DD transfer — The fourth phase of the

clock connects the negative terminal of C

2 to

ground and transfers the generated l0V across

2 to C4, the VDD storage capacitor. Again,

FEATURES…

The SP503 is a highly integrated serial trans-

ceiver that allows software control of its inter-

face modes. The SP503 offers hardware inter-

face modes for RS-232 (V.28), RS-422A (V.11),

RS-449, RS-485, V.35, and EIA-530. The inter-

face mode selection is done via an 8–bit switch;

four (4) bits control the drivers and four (4) bits

control the receivers. The SP503 is fabricated

using low–power BiCMOS process technology,

and incorporates a Sipex patented (5,306,954)

charge pump allowing +5V only operation. Each

device is packaged in an 80–pin Quad FlatPack

package.

The SP503 is ideally suited for wide area net-

work connectivity based on the interface modes

offered

and

the

driver

and

receiver

configurations. The SP503 has seven (7)

independent drivers and seven (7) independent

receivers. The seventh driver of the SP503

allows it to support applications which require

two separate clock outputs making it ideal for

DCE applications.

THEORY OF OPERATION

The SP503 is made up of four separate circuit

blocks — the charge pump, drivers, receivers,

and decoder. Each of these circuit blocks is

described in more detail below.

Charge–Pump

The charge pump is a Sipex patented design

(5,306,954) and uses a unique approach com-

VCC = +5V

–5V

+5V

VSS Storage Capacitor

VDD Storage Capacitor

–

Figure 1. Charge Pump Phase 1.

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