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SP6121EB 数据表(PDF) 3 Page - Sipex Corporation |
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SP6121EB 数据表(HTML) 3 Page - Sipex Corporation |
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3 / 6 page ![]() Rev 7/25/01 3 FIGURE 3. SP6121 Demo Board Schematic. Demo Board Component Selection The input capacitor, C6, can be either a ceramic or tantalum capacitor. Its choice depends on the user’s system input voltage transient. If the highest possible efficiency is required, a ceramic 47uF capacitor is recommended. The demo board circuit includes a Schottky Diode, D1, across the low side switch. It prevents Q2’s internal body diode from turning on and dissipating power during the nonoverlap time when both Q1 and Q2 are off. At a 500kHz switching frequency, these losses would decrease overall efficiency by 0.5 – 0.6%. The output voltage is set by the resistor divider: R3/R4. The output voltage is calculated using the following: REF OUT V R R V ÷ ø ö ç è æ + = 1 4 3 , where VREF = 1.25V. For the SP6121 demo board where VOUT = 2.5V. Choosing R4 equal to 10K, then K R R 10 4 3 = = The considerations, tradeoffs and calculations required to select the power MOSFETs (Q1, Q2), the inductor (L1), the input and output capacitors (C1, and C6, C8, and C9, L1 1.6uH C1 2.2uF 10 POWER OK U1 SP6121 1 2 7 6 5 4 3 8 Vcc GND NDRV ISET ISENSE COMP VFB PDRV GND C7 0.1uF U2 SP708 4 6 7 5 1 2 8 3 VCC PFI PFO GND RESET Reset NC MR Vin 9 C11 56pF 1,2,3,4 C9 470uF C8 470uF R4 10K TRIM C6 47uF D1 R2 2.3K R3 10K V out CERAMIC 7,8 R1 10K C2 56pF Q2 FDS6690A R5 10K C3 3.9nF R6 5.0 Q1 FDS6375 C10 0.1uF 5,6 C5 1.0uF +3.0V-7.0 V 2.5V |
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