TLF6365

June 1989

54LS42DM54LS42DM74LS42 BCDDecimal Decoders

General Description

These BCD-to-decimal decoders consist of eight inverters

and ten four-input NAND gates The inverters are connect-

ed in pairs to make BCD input data available for decoding

by the NAND gates Full decoding of input logic ensures

that all outputs remain off for all invalid (10 – 15) input condi-

tions

Features

Y

Diode clamped inputs

Y

Also for applications as 4-line-to-16-line decoders 3-

line-to-8-line decoders

Y

All outputs are high for invalid input conditions

Y

Alternate MilitaryAerospace device (54LS42) is avail-

able Contact a National Semiconductor Sales Office

Distributor for specifications

Connection Diagram

Dual-In-Line Package

TLF6365 – 1

Order Number 54LS42DMQB 54LS42FMQB

DM54LS42J DM54LS42W DM74LS42M or DM74LS42N

See NS Package Number J16A M16A N16E or W16A

Function Table

No

BCD Inputs

Decimal Outputs

D

C

B

A

0123456789

0

L

L

L

L

L

HHHHHHHHH

1

L

L

L

HH

L

H

HHHHHHH

2

L

L

H

L

H

H

L

HHHHHHH

3

L

L

HHHHH

L

H

HHHHH

4

L

H

L

L

H

HHH

L

HHHHH

5

L

H

L

HHHHHH

L

H

HHH

6

L

H

HLH

H

H

H

H

HLH

H

H

7

L

HHHHHHHHHH

L

H

H

8

H

L

L

L

H

HHHHHHH

L

H

9

H

L

L

HHHHHHHHHH

L

I

H

L

H

L

H

HHHHHHHHH

N

H

L

HHHHHHHHHHHH

V

HH

L

L

HHHHHHHHHH

A

HH

L

H

HHHHHHHHHH

L

HHH

L

H

HHHHHHHHH

I

HHHHHHHHHHHHHH

D

Logic Diagram

TLF6365 – 2

C1995 National Semiconductor Corporation

RRD-B30M105Printed in U S A