7

The simple guidelines for positioning the poles and zeros and for calculating the

component values for Type III compensation are as follows.

a.

Choose fco = fs / 10

b.

Calculate fp_LC

fp_LC = 1 / 2

π [(L) (C)] ^ 1/2

c.

Calculate fz_ESR

fz_ESR = 1 / 2

π (Resr) (Cout)

d.

Select R1 component value such that 50k

Ω ≤ R1 ≤ 100kΩ

e.

Calculate R2 base on the desired Vout

R2 = R1 / [(Vout / 0.80V) – 1]

f.

Select the ratio of Rz2 / R1 gain for the desired gain bandwidth

Rz2 = R1 (Vramp_pp / Vin_max) (fco / fp_LC)

g.

Calculate Cz2 by placing the zero at ½ of the output filter pole frequency

Cz2 = 1 /

π (Rz2) (fp_LC)

h.

Calculate Cp1 by placing the first pole at ESR zero frequency

Cp1 = 1 / 2

π (Rz2) (fz_ESR)

i.

Calculate Rz3 by setting the second pole at ½ of the switching frequency and the

second zero at the output filter double pole frequency

Rz3 = 2 (R1) (fp_LC) / fs

j.

Calculate Cz3 from Rz3 component value above

Cz3 = 1 /

π (Rz3) (fs)

k.

Choose 100pF

≤ Cf1 ≤ 220pF to stabilize the SP7652EU internal Error Amplify

As a particular example, consider for the following SP7652EB with a Type III Voltage

Loop Compensation component selections:

Vin = 5 to 15V

Vout = 3.30V @ 0 to 8A load

Select L = 1.5uH => yield

≈ 35% of maximum 8A output current ripple.

Select Cout = 47uF Ceramic capacitor (Resr

≈ 2mΩ)

fs = 600khz SP7652 internal Oscillator Frequency

Vramp_pp = 1.0V SP7652 internal Ramp Peak to Peak Amplitude

Step by step design procedures:

a.

fco = 600khz / 10 = 60khz

b.

fp_LC = 1 / 2

π [(1.5uH)(47uF)]^1/2 ≈ 20khz

c.

fz_ESR = 1 / 2

π (2mΩ)(47uF) ≈ 1.7Mhz