Date: 5/25/04

SP691A/693A/800L/800M Low Power Microprocessor Supervisor with Battery Switch-Over © Copyright 2004 Sipex Corporation

17

and connect CE

memory device as shown in Figure 26. The CE

input of each part then connects directly to the

chip-select logic, which does not have to gated

by the SP691A/693A/800L/800M devices.

Adding Hysteresis to the Power-Fail

Comparator

Hysteresis adds noise margin to the power-fail

comparator and prevents repeated triggering of

PFO when V

trip point. Figure 27 shows how to add hysteresis

to the power-fail comparator. Select the ratio of

R1 and R2 such that PFI sees 1.25V when V

IN

falls to the desired trip point (V

R3 adds hysteresis. It will typically be an order

of magnitude greater than R1 or R2. The

current through R1 and R2 should be at least

1

µA to ensure that the 25nA (max) PFI input

current does not shift the trip point. R3 should

be larger than 10k

Ω to prevent it from loading

down the PFO pin. Capacitor C1 adds additional

noise rejection.

Monitoring a Negative Voltage

The power-fail comparator can be used to monitor

a negative supply voltage using the circuit shown

in Figure 28. When the negative supply is valid,

PFO is low. When the negative supply voltage

drops, PFO goes high. This circuit's accuracy is

voltage, and resistors R1 and R2.

Backup-Battery Replacement

The backup battery may be disconnected while

are necessary to avoid spurious reset pulses.

Figure 26. Alternate Chip Enable Gating

GND

2

CE

CE

CE

CE

CE

CE

CE

CE

Active-HIGH

CE Logic Lines

for Memory Devices

13

4

12

on the connected number of RAMs, n.

Figure 27. Adding Hysteresis to the Power-Fail

Comparator

PFI

PFO

connect to µP

+5V

GND

PFO

+5V

0V

0V

*optional

1.25

=

5.0 - 1.25

+

1.25

1.25