5

Rev. 6/02/03

SP8024, 25, 26 200V/µs Integrated APC Amplifier

© Copyright 2003 Sipex Corporation

Layout and Routing Considerations

Special care must be taken when designing the

Flex or PCB for this part. The output peak

current requirement is in the order of 12.5mA

when driving 50pF of capacitive load with a

slew rate of 200V/s Therefore care must be

taken to provide low inductance, low resistance

paths for power and ground and output traces.

Supply coupling is also very important. Good

supply decoupling is important to ensure the

high frequency performance of the system by

eliminating supply lead inductance effects. The

decoupling capacitor C1 should be as close to

the part as possible. This capacitor should be

0.1

µF ceramic. C2 is optional to improve

decoupling and is recommended to be 1

µF tan-

Figure 2. Test and Evaluation PCB Layout for COB 8 Lead Package

Top

Bottom

talum. The layout of the PCB is pictured here.

Note the wide and short traces on the supply

lines.

The traces for the gain resistors R1 and R2 are

kept as short as possible to avoid excessive

parasitics. Any parasitics on these nodes will

limit the performance of the system. R1 and R2

are subminiature potentiometers in the applica-

tion. This is a single layer board done on FR4

material.

In order to minimize coupling capacitance into

the gain setting resistor nodes, it is also critical

traces associated with the gain-setting resistors.