Date: 5/25/04

SP691A/693A/800L/800M Low Power Microprocessor Supervisor with Battery Switch-Over © Copyright 2004 Sipex Corporation

13

RESET and RESET are asserted for the reset

timeout period (200ms nominal). WDO goes

to logic low and remains low until the next

transition at WDI. Refer to Figure 20. If WDI

is held high or low indefinitely, RESET and

RESET will generate 200ms pulses every 1.6s.

WDO has a 2 x TTL output characteristic.

Selecting an Alternative Watchdog

Timeout Period

The OSC

watchdog are reset timeout periods. Floating

OSC

selects the nominal 1.6s watchdog timeout

period and 200ms reset timout period.

Connecting OSC

connecting OSC

mal watchdog timeout period and a 1.6s timeout

period immediately after reset. The reset timeout

period remains 200ms. Refer to Figure 20.

Select alternative timeout periods by connecting

OSC

between OSC

driving OSC

be found in Figure 21 and Table 1.

Chip-Enable Signal Gating

The SP691A/693A/800L/800M devices

provide internal gating of chip-enable (CE)

signals, to prevent erroneous data from

corrupting the CMOS RAM in the event of a

power failure. During normal operation, the CE

gate is enabled and passes all CE transitions.

When reset is asserted, this path becomes

disabled, preventing erroneous data from

corrupting the CMOS RAM. The SP691A/

693A/800L/800M devices use a series transmission

gate from CE

The 10ns maximum CE propagation from CE

IN

to CE

800M devices to be used with most

µPs.

Chip-Enable Input

CE

while RESET and/or RESET are asserted.

During a power-down sequence where V

below the reset threshold, CE

impedance state when the voltage at CE

high or 12

µs after RESET is asserted,

whichever occurs first. Refer to Figure 19.

During a power-up sequence, CE

impedance until RESET is deasserted.

In the high-impedance mode, the leakage

currents into CE

In the low-impedance mode, the impedance of

CE

the load at CE

The propagation delay through the CE

transmission gate depends on both the source

impedance of the drive to CE

capacitive loading on CE

OUT

(see the

Chip-Enable Propagation Delay vs. CE

OUT

Load Capacitance graph in the Typical

Performance Characteristics section). The

CE propagation delay is defined from the 50%

point on CE

a 50

Ω driver and 50pF of load capacitance as in

Figure 22. For minimum propagation delay,

minimize the capacitive load at CE

a low output-impedance driver.

C

S

O

L

E

S

C

S

O

N

I

d

o

i

r

e

P

t

u

o

e

m

i

T

g

o

d

h

c

t

a

W

d

o

i

r

e

P

t

u

o

e

m

i

T

t

e

s

e

R

l

a

m

r

o

Nt

e

s

e

R

r

e

t

f

A

y

l

e

t

a

i

d

e

m

m

I

W

O

Lt

u

p

n

I

k

c

o

l

C

l

a

n

r

e

t

x

Es

k

c

o

l

c

4

2

0

1s

k

c

o

l

c

6

9

0

4s

k

c

o

l

c

8

4

0

2

W

O

Lr

o

t

i

c

a

p

a

C

l

a

n

r

e

t

x

Es

m

)

C

x

F

p

7

4

/

0

0

6

(c

e

s

)

C

x

f

p

7

.

4

/

4

.

2

(s

m

)

C

x

F

p

7

4

/

0

0

2

1

(

g

n

i

t

a

o

l

FW

O

Ls

m

0

0

1s

6

.

1s

m

0

0

2

g

n

i

t

a

o

l

Fg

n

i

t

a

o

l

Fs

6

.

1s

6

.

1s

m

0

0

2

Table 1. Reset Pulse Width and Watchdog Timeout Selections