OUT

OUT

1

2

LOAD

V

dV / dt

C

80k

(R

R ) R

=

´

W

+

P

P

OUT

OUT

LOAD

V

dV / dt

C

80k

R

=

´

W P

TPS732

www.ti.com

SBVS037P – AUGUST 2003 – REVISED DECEMBER 2015

Typical Applications (continued)

8.2.1 Design Requirements

addition to the internal 8-k

Ω resistor, presents the same impedance to the error amp as the 27-kΩ bandgap

reference output. This impedance helps compensate for leakages into the error amp terminals.

8.2.2 Detailed Design Procedure

8.2.2.1 Input and Output Capacitor Requirements

Although an input capacitor is not required for stability, it is good analog design practice to connect a 0.1-

μF to

1-

μF, low ESR capacitor across the input supply near the regulator. This capacitor counteracts reactive input

sources and improves transient response, noise rejection, and ripple rejection. A higher-value capacitor may be

necessary if large, fast rise-time load transients are anticipated or the device is located several inches from the

power source.

The TPS732 does not require an output capacitor for stability and has maximum phase margin with no capacitor.

It is designed to be stable for all available types and values of capacitors. In applications where multiple low ESR

ESR includes all parasitic resistances, including capacitor ESR and board, socket, and solder joint resistance. In

most applications, the sum of capacitor ESR and trace resistance meets this requirement.

8.2.2.2 Transient Response

The low open-loop output impedance provided by the NMOS pass element in a voltage follower configuration

allows operation without an output capacitor for many applications. As with any regulator, the addition of a

capacitor (nominal value 1

μF) from the OUT pin to ground reduces undershoot magnitude but increases its

the transient response.

The TPS732 does not have active pulldown when the output is overvoltage. This feature allows applications that

connect higher voltage sources, such as alternate power supplies, to the output. This feature also results in an

output overshoot of several percent if the load current quickly drops to zero when a capacitor is connected to the

output. The duration of overshoot can be reduced by adding a load resistor. The overshoot decays at a rate

(Fixed voltage versions)

(4)

(Adjustable voltage version)

(5)

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