TPS732

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SBVS037P – AUGUST 2003 – REVISED DECEMBER 2015

6.4 Thermal Information

DRB [SON]

DCQ

DBV [SOT23]

UNIT

[SOT223]

8 PINS

6 PINS

5 PINS

Junction-to-ambient thermal resistance

58.3

53.1

205.9

Junction-to-case (top) thermal resistance

93.8

35.2

119

Junction-to-board thermal resistance

72.8

7.8

35.4

°C/W

Junction-to-top characterization parameter

2.7

2.9

12.7

Junction-to-board characterization parameter

25

7.7

34.5

Junction-to-case (bottom) thermal resistance

5

N/A

N/A

(1)

For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.

(2)

For thermal estimates of this device based on PCB copper area, see the TI PCB Thermal Calculator.

(3)

Thermal data for the DRB, DCQ, and DRV packages are derived by thermal simulations based on JEDEC-standard methodology as

specified in the JESD51 series. The following assumptions are used in the simulations:

(a)

i. DRB: The exposed pad is connected to the PCB ground layer through a 2 × 2 thermal via array.

(b) i. DRB: The top and bottom copper layers are assumed to have a 20% thermal conductivity of copper representing a 20% copper

coverage.

coverage.

(c) These data were generated with only a single device at the center of a JEDEC high-K (2s2p) board with 3-inch × 3-inch copper area.

To understand the effects of the copper area on thermal performance, see the Power Dissipation section of this data sheet.

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