SP8056

Rev 1 (9-17-03): SP8056 – High Speed 10 Channel PDIC

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GAIN MODE SELECTION

Gain Mode

Gain Factor

Logic level

Gain1

Gain2

Gain3

Low

Low

DC

RW-read

128

Low

Z

Low

Low

Z

High

R-read

32

Low

High

DC

RW-write(speed 1)

16

High

Low

High

RW-write(speed 2)

12

High

Low

Z

RW-write(speed 3)

8

High

Low

Low

RW-write(speed 4)

6

High

Z

Low

R-write(speed 1)

4

High

Z

High

R-write(speed 2)

3

High

High

Z

R-write(speed 3)

2

High

High

High

R-write(speed 4)

1

High

High

Low

Adjustment mode

32

High

Z

Z

Sleep mode (output=High-Z)

Low

Z

Z

Note: DC - Don't Care, Z - High impedance

PIN ASSIGNMENTS

Pin #

Pin Name

Pin Function

1

Vs

Reference voltage. Bypass to GND with ceramic capacitor 0.1uF

2

Gain 2

Logic input of Gain Controller. Allows three states – low, high, and floating - Z

3

Gain 1

Logic input of Gain Controller. Allows two states – low and high

4

Gain 3

Logic input of Gain Controller. Allows three states – low, high and floating - Z

5

EF

Output of EF channel (sum of E + F sensor signals). In Adjustment mode it is output

of E channel

6

SAD

Output of SAD channel. In Adjustment mode it is output of F channel

7

GH

Output of GH channel (sum of G + H sensor signals). In Adjustment mode it is output

of G channel

8

SBC

Output of SBC channel. In Adjustment mode it is output of H channel

9

GND

Ground pin

10

A

Output of A channel

11

D

Output of D channel

12

B

Output of B channel

13

C

Output of C channel

14

RF-

Output of RF- channel. RF- = - (A + B +C + D + EF + GH). In Adjustment mode RF-

= - (A + B + C + D + E + F + G + H)

15

RF+

Output of RF+ channel. RF+ = A + B + C + D + EF + GH. In Adjustment mode RF+ =

A + B + C + D + E + F + G + H

16

Vcc

Supply voltage. Bypass to GND with ceramic capacitor 0.1uF

BOARD LAYOUT AND GROUNDING

To obtain the best performance from the SP8056, a printed circuit board with ground plane is

required. High quality, low series resistance ceramic 0.1uF bypass capacitors should be used at

the Vcc and Vs pins (pins 1 and 16). These capacitors must be located as close to the pins as

possible. The traces connecting the pins and the bypassing capacitors must be kept short and

should be made as wide as possible.