Switching Characteristics

Symbol

Parameter

9338 (MIL)

DM9338 (COM)

Units

Min

Max

Min

Max

Propagation Delay

40

13

40

ns

35

18

35

Propagation Delay

45

25

45

ns

50

25

50

Propagation Delay

35

18

35

ns

30

13

30

Functional Description

The 9338 8-bit multiple port register can be considered a 1-

bit slice of eight high speed working registers Data can be

written into any one and read from any two of the eight

locations simultaneously Masterslave operation eliminates

all race problems associated with simultaneous readwrite

activity from the same location When the clock input (CP) is

selected master This selection is accomplished by coding

the three write input select lines (A0 – A2) appropriately

Data is stored synchronously with the rising edge of the

clock pulse

The information for each of the two slaved (output) latches

is selected by two sets of read address inputs (B0 – B2 and

C0 – C2) The information enters the slave while the clock is

HIGH and is stored while the clock is LOW If Slave Enable

is LOW (SLE) the slave latches are continuously enabled

The input bit selection and the two output bit selections can

be accomplished independently or simultaneously The data

flows into the device is demultiplexed according to the state

of the write address lines and is clocked into the selected

latch The eight latches function as masters and store the

input data The two output latches are slaves and hold the

data during the read operation The state of each slave is

determined by the state of the master selected by its associ-

ated set of read address inputs

The method of parallel expansion is shown in

Figure a One

9338 is needed for each bit of the required word length The

read and write input lines should be connected in common

on all of the devices This register configuration provides

two words of n-bits each at one time where n devices are

connected in parallel

Logic Symbol

TLF9794 – 2

TLF9794 – 4

FIGURE a Parallel Expansion

3