Symbol

Parameter

Conditions

96L02 (Mil)

DM96L02 (Com)

Units

Min

Max

Min

Max

Propagation Delay I0toQ

75

80

ns

I1 to Q

Propagation Delay I0toQ

62

65

ns

I1 to Q

Propagation Delay CD to Q

100

ns

CD to Q

Functional Block Diagram

TLF10203 – 3

Operation Notes

1 TRIGGERINGcan be accomplished by a positive-going

transition on pin 4 (12) or a negative-going transition on

pin 5 (11) Triggering begins as a signal crosses the input

whose unbalanced cross-coupling causes it to assume a

preferred state As the latch output goes LOW it disables

the gates leading to the Q output and through an invert-

er turns on the capacitor discharge transistor The invert-

ed signal is also fed back to the latch input to change its

state and effectively end the triggering action thus the

latch and its associated feed-back perform the function of

a differentiator

The emitters of the latch transistors return to ground

through an enabling transistor which must be turned off

between successive triggers in order for the latch to pro-

ceed through the proper sequence when triggering is de-

sired Pin 5 (11) must be HIGH in order to trigger at pin 4

(12) conversely pin 4 (12) must be LOW in order to trig-

ger at pin 5 (11)

2 RETRIGGERINGIn a normal cycle triggering initiates a

rapid discharge of the external timing capacitor followed

by a ramp voltage run-up at pin 2 (14) The delay will time

out when the ramp voltage reaches the upper trigger

point of a Schmitt circuit causing the outputs to revert to

the quiescent state If another trigger occurs before the

ramp voltage reaches the Schmitt threshold the capaci-

tor will be discharged and the ramp will start again without

having disturbed the output The delay period can there-

fore be extended for an arbitrary length of time by insur-

ing that the interval between triggers is less than the de-

lay time as determined by the external capacitor and re-

sistor

3 NON-RETRIGGERABLE OPERATIONRetriggering can

be inhibited logically by connecting pin 6 (10) back to pin

4 (12) or by connecting pin 7 (9) back to pin 5 (11) Either

hook-up has the effect of keeping the latch-enabling tran-

sistor turned on during the delay period which prevents

the input latch from cycling as discussed above in the

section on triggering

tional block diagram To minimize stray capacitance and

possible to the circuit In applications which require re-

mote trimming of the pulse width as with a variable resis-

variable resistor the fixed resistor should be located as

Figure a

5 SETUP AND RELEASE TIMESThe setup times listed

below are necessary to allow the latch-enabling transistor

to turn off and the node voltages within the input latch to

stabilize thus insuring proper cycling of the latch when

the next trigger occurs The indicated release times

(equivalent to trigger duration) allow time for the input

latch to cycle and its signal to propagate

Input to Pin 5 (11)

TLF10203 – 4

3