PI6C49016 datasheet(2/16 Pages) PERICOM

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PI6C49016

Rev. B

06/25/13

PI6C49016

Low Power Networking Clock Generator

Pin Description

Pin#

Pin Name

Pin Type

Pin Description

VDD

Power

3.3V Supply Pin

GND

Power

Ground

VDD

Power

3.3V Supply Pin

GND

Power

Ground

VDD

Power

3.3V Supply Pin

SCLK

Input

SMBus clock input

SDATA

I/O

SMBus data input

GND

Power

Ground

80M

Output

80 MHz LVCMOS output. Tri-state with weak pull-

down when disabled

VDD

Power

3.3V Supply Pin

VDD

Power

3.3V Supply Pin

GNDX

Power

Ground

PD_RESET

Input

Global reset input powers down PLLs plus tri-states

outputs and sets the I2C tables to their default state

when pulled low. Controlled by external POR

Pin List

Power Grouping

Pins

Group Description

1, 3, 7, 30 Power for PCIe clocks

Power for 80 MHz PLL and output

13, 22, 28 Power for 60/66 MHz PLL and outputs

Power for crystal oscillator

Output Power for 125 MHz

Power for 125 MHz PLL

35, 37

Digital power

GND

40-pin QFN

VDD

GND

VDD

GND

VDD

GND

VDD

SCLK

SDATA

GND

66.66M

VDD

GND

VDD

13-0102

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PI6C49016 数据表(PDF) 2 Page - Pericom Semiconductor Corporation

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