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TLC59581 数据表(PDF) 21 Page - Texas Instruments |
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TLC59581 数据表(HTML) 21 Page - Texas Instruments |
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21 / 28 page ![]() TLC59581, TLC59582 www.ti.com SLVSCZ9A – OCTOBER 2015 – REVISED NOVEMBER 2015 10 Application and Implementation NOTE Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality. See application note: Build High Density, High Refresh Rate, Multiplexing LED Panel with TLC59581, SLVA744 available on ti.com 11 Power Supply Recommendations Decouple the VCC power supply voltage by placing a 0.1-µF ceramic capacitor close to VCC pin and GND plane. Depending on panel size, several electrolytic capacitors must be placed on the board equally distributed to get a well regulated LED supply voltage (VLED). VLED voltage ripple must be less than 5% of its nominal value. Furthermore, set the VLED voltage as calculated by equation: VLED > Vf + 0.4 V (10 mA constant current example) where • Vf = maximum forward voltage of LED (3) 12 Layout 12.1 Layout Guidelines 1. Place the decoupling capacitor near the VCC pin and GND plane. 2. Place the current programming resistor RIREF close to IREF pin and IREFGND pin. 3. Route the GND pattern as widely as possible for large GND currents. Maximum GND current is approximately 1.2 A. 4. Routing between the LED cathode side and the device OUTXn pin should be as short and straight as possible to reduce wire inductance. 5. The PowerPAD™ must be connected to GND plane because the pad is used as power ground pin internally, there is a large current flow through this pad when all channels turn on. Furthermore, this pad should be connected to a heat sink layer by thermal via to reduce device temperature. One suggested thermal via pattern is shown in the Device Layout Example. For more information about suggested thermal via pattern and via size, see PowerPAD Thermally Enhanced Package, SLMA002G. 6. MOSFETS must be placed in the in the middle of the board, which should be laid out as symmetrically as possible. Copyright © 2015, Texas Instruments Incorporated Submit Documentation Feedback 21 TLC59582 |
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