5

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PI6CFGL201B

RevB

03/16/16

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PI6CFGL201B

2-Output Low Power PCIE Gen 1-2-3 Clock Generator

Electrical Characteristics–Input/Supply/Common Parameters

(Based on T

o

C; VDD = 3.3V +/-10%; VDDO = 1.8V +/-10%, See Test Loads for Loading Conditions)

Symbol Parameters

Condition

Min.

Type Max.

Units

V

DDX

Supply voltage for core, analog

3.0

3.3

3.6

V

V

DDO

Supply voltage outputs

1.05

1.8

3.3

V

T

A

Ambient Operating

-40

25

85

°C

V

IH

Single-ended inputs, except SMBus, SS_EN_tri

0.65 V

DD

V

V

V

IM

SS_EN_tri

0.4 V

DD

0.6 V

DD

V

V

IL

Single-ended inputs, except SMBus, SS_EN_tri

-0.3

0.35 V

DD

V

V

T+

Schmitt Trigger Postive

Single-ended inputs, except SS_EN_tri

0.5 V

DD

0.6 V

DD

V

V

T-

Schmitt Trigger Negative

Single-ended inputs, except SS_EN_tri

0.4 V

DD

0.5 V

DD

V

V

H

V

0.05 V

DD

0.2 V

DD

V

V

OH

Single-ended outputs, except SMBus. I

-2mA

V

DD

-0.45

V

V

OL

Single-ended outputs, except SMBus. I

-2mA

0.45

V

I

IN

Single-ended inputs, V

(exclude XTAL_IN pin)

-5

5

uA

I

INP

Single-ended inputs

V

V

resistors

-200

200

uA

fin

XTAL, or XTAL_IN

23

25

26

MHz

Lpin

7

nH

C

IN

Control Inputs

1.5

5

pF

Cout

Output pin capacitance

6

pF

t

STAB

Clock output Stabiliza-

From V

stabilization or de-assertion of CKPWRGD_

PD# to 1st clock

0.6

1

ms

f

MODIN

Input SS Modulation

Allowable Frequency

(Triangular Modulation)

30

31.500 33

kHz

t

LATOE#

CLK start after OE# assertion

CLK stop after OE# deassertion

1

3

clocks

t

DRVPD

CLK output enable after

CKPWRGD_PD# de-assertion

300

us

15-0134