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PI6LC48P0401

Rev.D

11/7/2014

PI6LC48P0401

4-Output LVPECL Networking Clock Generator

Pinout Table

Pin No.

Pin Name

I/O Type

Description

1, 2

CLK1#, CLK1

Output

LVPECL Output Clock 1

3, 22

Power

Output supply pins

4, 5

CLK0, CLK0# Output

LVPECL Output Clock 0

6

M_reset

Input

Pulldown

Active HIGH Master Reset. When logic HIGH, the internal dividers are

reset causing the true outputs Qx to go low and the inverted outputs

nQx to go high. When logic LOW, the internal dividers and outputs are

enabled.

7

PLL_Bypass

Input

Pulldown

Selects either the PLL or the active input reference to be routed to the

output dividers. When LOW, selects PLL (PLL enable). When HIGH,

selects the reference clock (PLL bypass).

8

NC

Not connected

9

Power

Analog power supply

10,

12

N_SEL0,

N_SEL1

Input

Pulldown Frequency select pins

11, 18

Power

Core power supply

13,

14

XTAL_OUT,

XTAL_IN

Output /

Input

Parallel resonant crystal interface. XTAL_OUT is the output, and

XTAL_IN is the input.

15, 19

GND

Power

Ground

16

Ref_IN

Input

Pulldown CMOS reference clock input

17

IN_SEL

Input

Pulldown

Selects between the single-ended Ref_IN or crystal interface as the

PLL reference source. When HIGH, selects Ref_IN. When LOW selects

XTAL inputs.

20, 21

CLK3#, CLK3 Output

LVPECL Output Clock 3

23, 24

CLK2, CLK2# Output

LVPECL Output Clock 2

Pin Configuration

1

2

3

CLK0

4

CLK0#

5

6

PLL_Bypass

7

IN_SEL

8

M_reset

CLK2#

CLK3

GND

NC

24

23

22

21

20

19

18

17

CLK1#

CLK1

CLK3#

CLK2

Ref_IN

9

16

GND

10

N_SEL0

15

XTAL_IN

11

14

XTAL_OUT

12

13

N_SEL1

14-0203