PB-MX860-January 21, 2014

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1

Features

Applications

Ordering Information

Description

The MX860 is a selectable 240, 256, or 268 bit long;

2-bit wide; serial-input parallel-output digital shift

register with level conversion on each parallel output.

bus simultaneously inputs 4 groups of 2 bits each.

The MX860 consists of a selectable length

Bidirectional Input Register, Transfer Latch, and

268-bit Level Shifter / Output Driver. Each OUT pin is

the D0...D7 logic levels clocked into the MX860,

modified by the OE pin.

The MX860 is designed to operate over a temperature

range of -40°C to +85°C, and is available as Gold

Bumped Die in Wafer Form or Waffle Pack, and 48mm

Super-Wide Tape Carrier Package.

Figure 1. Functional Block Diagram

Part

Description

MX860WB

Gold Bumped Die / Wafer Form

MX860XB

Gold Bumped Die / Waffle Pack

MX860TC

48mm Super Wide Tape Carrier

OUT1

OUT2

. . .

OUT267 OUT268

VPOS

VSS

LEVEL SHIFTER / DRIVER

VNEG

OE

DECODE

LE

LATCH

4-way Interleaved

2-bit Register

4x(1 - 60)

61 - 64

65 - 67

Stages

Data path when

when

SHR = 1

SHR = 0

mode 240

256

268

Clock

D(7..0)

CONTROL LOGIC

Direction

SHR

MODE1

MODE0

CE

CL

MX860

+/-15V ePaper Source Driver