PI7C8150BMA-33 datasheet(61/107 Pages) PERICOM

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PI7C8150B

ASYNCHRONOUS 2-PORT PCI-TO-PCI BRIDGE

Page 61 of 107

April 2015 – Revision 2.1

The initiator leaves the LOCK_L signal de-asserted during the address phase and asserts

LOCK_L one clock cycle later. Once a data transfer is completed from the target, the target

lock has been achieved.

7.2.1

LOCKED TRANSACTIONS IN DOWNSTREAM DIRECTION

Locked transactions can cross PI7C8150B only in the downstream direction, from the

primary bus to the secondary bus.

When the target resides on another PCI bus, the master must acquire not only the lock on

its own PCI bus but also the lock on every bus between its bus and the target’s bus. When

PI7C8150B detects on the primary bus, an initial locked transaction intended for a target on

the secondary bus, PI7C8150B samples the address, transaction type, byte enable bits, and

parity, as described in Section 3.5.4. It also samples the lock signal. If there is a lock

established between 2 ports or the target bus is already locked by another master, then the

current lock cycle is retried without forward. Because a target retry is signaled to the

initiator, the initiator must relinquish the lock on the primary bus, and therefore the lock is

not yet established.

The first locked transaction must be a memory read transaction. Subsequent locked

transactions can be memory read or memory write transactions. Posted memory write

transactions that are a part of the locked transaction sequence are still posted. Memory read

transactions that are a part of the locked transaction sequence are not pre-fetched.

When the locked delayed memory read request is queued, PI7C8150B does not queue any

more transactions until the locked sequence is finished. PI7C8150B signals a target retry to

all transactions initiated subsequent to the locked read transaction that are intended for

targets on the other side of PI7C8150B. PI7C8150B allows any transactions queued before

the locked transaction to complete before initiating the locked transaction.

When the locked delayed memory read request transaction moves to the head of the

delayed transaction queue, PI7C8150B initiates the transaction as a locked read transaction

by de-asserting LOCK_L on the target bus during the first address phase, and by asserting

LOCK_L one cycle later. If LOCK_L is already asserted (used by another initiator),

PI7C8150B waits to request access to the secondary bus until LOCK_L is de-asserted

when the target bus is idle. Note that the existing lock on the target bus could not have

crossed PI7C8150B. Otherwise, the pending queued locked transaction would not have

been queued. When PI7C8150B is able to complete a data transfer with the locked read

transaction, the lock is established on the secondary bus.

When the initiator repeats the locked read transaction on the primary bus with the same

address, transaction type, and byte enable bits, PI7C8150B transfers the read data back to

the initiator, and the lock is then also established on the primary bus.

For PI7C8150B to recognize and respond to the initiator, the initiator’s subsequent

attempts of the read transaction must use the locked transaction sequence (de-assert

LOCK_L during address phase, and assert LOCK_L one cycle later). If the LOCK_L

sequence is not used in subsequent attempts, a master timeout condition may result. When

a master timeout condition occurs, SERR_L is conditionally asserted (see Section 6.4), the

read data and queued read transaction are discarded, and the LOCK_L signal is de-asserted

on the target bus.

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