Functional Description

Operating on a single +5V supply, the ADC14061 uses a

pipelined architecture and has error correction circuitry and a

calibration mode to help ensure maximum performance at all

times.

Balanced analog signals with a peak-to-peak voltage equal

to the input reference voltage, V

the common mode input voltage, V

(13 bits plus sign). Neglecting offsets, positive input signal

voltages (V

data and negative input signal voltages (V

produce negative output data. The input signal can be digi-

tized at any clock rate between 300 Ksps and 2.5 Msps.

Input voltages below the negative full scale value will cause

the output word to take on the negative full scale value of

10,0000,0000,0000. Input voltage above the positive full

scale value will cause the output word to take on the positive

full scale value of 01,1111,1111,1111.

The output word rate is the same as the clock frequency. The

analog input voltage is acquired at the falling edge of the

clock and the digital data for that sample is delayed by the

pipeline for 13 clock cycles plus t

put is undefined if the chip is being reset or is in the calibra-

tion mode. The output signal may be inhibited by the RD pin

while the converter is in one of these modes.

The RD pin must be low to enable the digital outputs. A logic

low on the power down (PD) pin reduces the converter

power consumption to less than two milliwatts.

Applications Information

1.0 OPERATING CONDITIONS

We recommend that the following conditions be observed for

operation of the ADC14061:

4.75V

≤ V

5.25V

≤ V

3.0V

≤ V

0.3MHz

≤ f

V

V

V

1.1 The Analog Inputs

The ADC14061 has two analog signal inputs, V

These two pins form a balanced signal input. There are two

reference pins, V

fully differential input reference.

1.2 Reference Inputs

V

effective reference voltage, V

these two voltages:

V

The operational voltage range of V

+3.0 Volts. The operational voltage range of V

ground to 1.0V. For best performance, the difference be-

tween V

of 1.8V to 2.2V. Reducing the reference voltage below 1.8V

will decrease the signal-to-noise ratio (SNR) of the

ADC14061. Increasing the reference voltage (and, conse-

quently, the input signal swing) above 2.2V will increase

THD.

V

V

this pin with 0.1µF capacitor to ground. Do not load this pin.

It is very important that all grounds associated with the refer-

ence voltage make connection to the analog ground plane at

a single point to minimize the effects of noise currents in the

gound path.

1.3 Signal Inputs

The signal inputs are V

is defined as

V

Figure 3 indicates the relationship between the input voltage

and the reference voltages.

Figure 4 shows the expected in-

put signal range.

The ADC14061 performs best with a balanced input cen-

tered around V

V

each signal input pin should be centered on the V

The two V

out of phase from each other. As a simple check to ensure

this, be certain that the average voltage at the ADC iinput

pins is equal to V

impedance less than 100 Ohms.

DS100103-17

FIGURE 3. Typical Input to Reference Relationaship.

DS100103-18

FIGURE 4. Expected Input Signal Range.

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